1d4a427400
These are critical for display performance and should not be balanced in order to improve latency and responsiveness. And also affine them. Change-Id: If49ecb8757d133a7fad0d7946837b35403e57c2a Signed-off-by: Sandeep P S <sandymankara11@gmail.com>
10 lines
500 B
Plaintext
10 lines
500 B
Plaintext
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# Copyright (c) 2019 Qualcomm Technologies, Inc.
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# All Rights Reserved.
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# Confidential and Proprietary - Qualcomm Technologies, Inc.
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################################################################################################################################
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PRIO=1,1,1,1,0,0,0,0
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#arch_timer, arm-pmu, arch_mem_timer,msm_drm,kgsl_3d0_irq
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IGNORED_IRQ=27,23,38,115,332
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