362 lines
12 KiB
Plaintext
362 lines
12 KiB
Plaintext
###############################################################################
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## Modified by Motorola Mobility LLC
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## Version : 3.5.2 (2016/06/21)
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## added RF Blk 4 (21 to 22) and rf blk 5 (from 47 to 77) and rf blk 6 (from 10 to 00)
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## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
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## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
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## CLIF_ANA_TX_AMPLITUDE_REG_TYPE_B_TERMINAL_M
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## CLIF_ANA_TX_AMPLITUDE_REG_TYPE_B_TERMINAL_M change 90 to 00
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###############################################################################
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# Application options
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# Logging Levels
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# NXPLOG_DEFAULT_LOGLEVEL 0x01
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# ANDROID_LOG_DEBUG 0x03
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# ANDROID_LOG_WARN 0x02
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# ANDROID_LOG_ERROR 0x01
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# ANDROID_LOG_SILENT 0x00
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#
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NXPLOG_EXTNS_LOGLEVEL=0x03
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NXPLOG_NCIHAL_LOGLEVEL=0x03
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NXPLOG_NCIX_LOGLEVEL=0x03
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NXPLOG_NCIR_LOGLEVEL=0x03
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NXPLOG_FWDNLD_LOGLEVEL=0x03
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NXPLOG_TML_LOGLEVEL=0x03
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###############################################################################
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# Nfc Device Node name
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NXP_NFC_DEV_NODE="/dev/pn544"
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###############################################################################
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# Extension for Mifare reader enable
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MIFARE_READER_ENABLE=0x01
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###############################################################################
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# Vzw Feature enable
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VZW_FEATURE_ENABLE=0x01
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###############################################################################
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# File name for Firmware
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NXP_FW_NAME="libpn548ad_fw.so"
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###############################################################################
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# System clock source selection configuration
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#define CLK_SRC_XTAL 1
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#define CLK_SRC_PLL 2
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NXP_SYS_CLK_SRC_SEL=0x01
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###############################################################################
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# System clock frequency selection configuration
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#define CLK_FREQ_13MHZ 1
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#define CLK_FREQ_19_2MHZ 2
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#define CLK_FREQ_24MHZ 3
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#define CLK_FREQ_26MHZ 4
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#define CLK_FREQ_38_4MHZ 5
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#define CLK_FREQ_52MHZ 6
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NXP_SYS_CLK_FREQ_SEL=0x04
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###############################################################################
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# The timeout value to be used for clock request acknowledgment
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# min value = 0x01 to max = 0x06
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NXP_SYS_CLOCK_TO_CFG=0x01
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###############################################################################
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# NXP proprietary settings
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NXP_ACT_PROP_EXTN={2F, 02, 00}
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###############################################################################
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# NFC forum profile settings
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NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
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###############################################################################
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# NFCC Configuration Control
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# Allow NFCC to manage RF Config 0x01
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# Don't allow NFCC to manage RF Config 0x00
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NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01}
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###############################################################################
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# Standby enable settings
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NXP_CORE_STANDBY={2F, 00, 01, 01}
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###############################################################################
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# NXP TVDD configurations settings
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# Allow NFCC to configure External TVDD, There are currently three
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#configurations (1, 2 and 3) are supported, out of them only one can be
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#supported.
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NXP_EXT_TVDD_CFG=0x02
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#config1:SLALM, 3.3V for both RM and CM
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NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00}
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#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
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#monitoring 5V from DCDC, 4.7V for both RM and CM, DCDCWaitTime=4.2ms
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NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 64, 0A}
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#config3: use DCDC in CE, use Tx_Pwr_Req, SLALM, monitoring 5V from DCDC,
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#DCDCWaitTime=4.2ms
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NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_1={
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20, 02, 1E, 2,
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A0, 1D, 11, 54, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
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A0, 0D, 06, 06, 03, 00, 6F, 00, 20
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_2={
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20, 02, 13, 02,
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A0, 0D, 06, 06, 30, B0, 00, 10, 00,
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A0, 0D, 06, 7C, 30, B0, 00, 10, 00
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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NXP_RF_CONF_BLK_3={
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20, 02, 07, 01,
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A0, 0D, 03, 00, 40, 03
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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# RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG change from 21 to 22
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NXP_RF_CONF_BLK_4={
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20, 02, 1D, 04,
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A0, 0D, 04, 34, 44, 22, 00,
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A0, 0D, 04, 46, 44, 22, 00,
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A0, 0D, 04, 56, 44, 22, 00,
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A0, 0D, 04, 5C, 44, 26, 00
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform, Min_level
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# RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG change from 47 to 77
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NXP_RF_CONF_BLK_5={
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20, 02, 0A, 01,
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A0, 0D, 06, 34, 2D, 24, 77, 0C, 00
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}
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###############################################################################
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# NXP RF configuration ALM/PLM settings
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# This section needs to be updated with the correct values based on the platform
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# RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG change from 10 to 00
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# RF_CLIF_CFG_BR_106_T_TXB
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NXP_RF_CONF_BLK_6={
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20, 02, 2E, 05,
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A0, 0D, 06, 32, 42, F8, 00, FF, FF,
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A0, 0D, 06, 44, 42, 88, 00, FF, FF,
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A0, 0D, 06, 54, 42, 88, 00, FF, FF,
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A0, 0D, 06, 5A, 42, 90, 00, FF, FF,
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A0, 0D, 06, 98, 42, 00, 00, FF, FF
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}
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###############################################################################
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## Set configuration optimization decision setting
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## Enable = 0x01
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## Disable = 0x00
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NXP_SET_CONFIG_ALWAYS=0x01
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###############################################################################
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# Core configuration extensions
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# It includes
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# Wired mode settings A0ED, A0EE
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# Tag Detector A040, A041, A043
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# Low Power mode A007
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# Clock settings A002, A003
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# PbF settings A008
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NXP_CORE_CONF_EXTN={20, 02, 1D, 07,
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A0, EC, 01, 01,
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A0, ED, 01, 00,
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A0, 5E, 01, 01,
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A0, 40, 01, 01,
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A0, DD, 01, 2D,
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A0, 41, 01, 02,
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A0, 96, 01, 01
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}
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# A0, 41, 01, 02,
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# A0, 43, 01, 04,
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# A0, 02, 01, 01,
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# A0, 03, 01, 11,
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# A0, 07, 01, 03,
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# A0, 08, 01, 01
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# }
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###############################################################################
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# Core configuration rf field filter settings to enable set to 01 to disable set to 00 last bit
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NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 01
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}
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###############################################################################
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# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00
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NXP_I2C_FRAGMENTATION_ENABLED=0x00
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###############################################################################
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# Core configuration settings
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NXP_CORE_CONF={ 20, 02, 31, 0F,
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28, 01, 00,
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21, 01, 00,
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30, 01, 08,
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31, 01, 03,
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33, 04, 01, 02, 03, 04,
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54, 01, 06,
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50, 01, 02,
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5B, 01, 00,
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60, 01, 0E,
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80, 01, 01,
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81, 01, 01,
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82, 01, 0E,
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18, 01, 01,
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32, 01, 60,
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38, 01, 01
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}
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###############################################################################
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# Mifare Classic Key settings
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#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
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# A0, 52, 06, D3, F7, D3, F7, D3, F7,
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# A0, 53, 06, FF, FF, FF, FF, FF, FF,
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# A0, 54, 06, 00, 00, 00, 00, 00, 00}
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###############################################################################
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# Default SE Options
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# No secure element 0x00
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# eSE 0x01
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# UICC 0x02
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NXP_DEFAULT_SE=0x02
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###############################################################################
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#Enable SWP full power mode when phone is power off
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NXP_SWP_FULL_PWR_ON=0x00
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###############################################################################
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#### Select the CHIP ####
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#PN547C2 0x01
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#PN65T 0x02
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#PN548AD 0x03
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#PN66T 0x04
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NXP_NFC_CHIP=0x03
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###############################################################################
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# CE when Screen state is locked
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# Disable 0x00
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# Enable 0x01
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NXP_CE_ROUTE_STRICT_DISABLE=0x01
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#Timeout in secs to get NFCEE Discover notification
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NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20
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NXP_DEFAULT_NFCEE_TIMEOUT=0x06
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#Timeout in secs
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NXP_SWP_RD_START_TIMEOUT=0x0A
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#Timeout in secs
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NXP_SWP_RD_TAG_OP_TIMEOUT=0x01
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###############################################################################
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#Set the default AID route Location :
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#This settings will be used when application does not set this parameter
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# host 0x00
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# eSE 0x01
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# UICC 0x02
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DEFAULT_AID_ROUTE=0x02
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###############################################################################
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#Set the Mifare Desfire route Location :
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#This settings will be used when application does not set this parameter
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# host 0x00
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# eSE 0x01
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# UICC 0x02
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DEFAULT_DESFIRE_ROUTE=0x02
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###############################################################################
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#Set the Mifare CLT route Location :
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#This settings will be used when application does not set this parameter
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# host 0x00
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# eSE 0x01
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# UICC 0x02
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DEFAULT_MIFARE_CLT_ROUTE=0x02
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###############################################################################
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#Set the default AID Power state :
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#This settings will be used when application does not set this parameter
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# bit pos 0 = Switch On
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# bit pos 1 = Switch Off
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# bit pos 2 = Battery Off
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# bit pos 3 = Screen Lock
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# bit pos 4 = Screen Off
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DEFAULT_AID_PWR_STATE=0x9
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###############################################################################
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#Set the Mifare Desfire Power state :
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#This settings will be used when application does not set this parameter
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# bit pos 0 = Switch On
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# bit pos 1 = Switch Off
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# bit pos 2 = Battery Off
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# bit pos 3 = Screen Lock
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# bit pos 4 = Screen Off
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DEFAULT_DESFIRE_PWR_STATE=0x1B
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###############################################################################
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#Set the Mifare CLT Power state :
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#This settings will be used when application does not set this parameter
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# bit pos 0 = Switch On
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# bit pos 1 = Switch Off
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# bit pos 2 = Battery Off
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# bit pos 3 = Screen Lock
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# bit pos 4 = Screen Off
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DEFAULT_MIFARE_CLT_PWR_STATE=0x1B
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###############################################################################
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# AID Matching platform options
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# AID_MATCHING_L 0x01
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# AID_MATCHING_K 0x02
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AID_MATCHING_PLATFORM=0x01
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###############################################################################
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#CHINA_TIANJIN_RF_SETTING
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#Enable 0x01
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#Disable 0x00
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NXP_CHINA_TIANJIN_RF_ENABLED=0x01
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###############################################################################
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#SWP_SWITCH_TIMEOUT_SETTING
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# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
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# Timeout in milliseconds, for example
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# No Timeout 0x00
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# 10 millisecond timeout 0x0A
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NXP_SWP_SWITCH_TIMEOUT=0x0A
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###############################################################################
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#Dynamic RSSI feature enable
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# Disable 0x00
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# Enable 0x01
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NXP_AGC_DEBUG_ENABLE=0x00
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###############################################################################
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#Config to allow adding aids
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#NFC on/off is required after this config
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#1 = enabling adding aid to NFCC routing table.
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#0 = disabling adding aid to NFCC routing table.
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NXP_ENABLE_ADD_AID=0x01
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################################################################################
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# Enable/Disable checking default proto SE Id
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# Disable 0x00
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# Enable 0x01
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NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01
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###############################################################################
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# UICC mode supported
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# Disable 0x00
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# Enable 0x01
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NXP_DUAL_UICC_ENABLE=0x00
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