############################################################################### ## Modified by Motorola Mobility LLC ## Version : 4.2 (2017/05/23) ## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn548) ## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn548) ############################################################################### # Application options # Logging Levels # NXPLOG_DEFAULT_LOGLEVEL 0x01 # ANDROID_LOG_DEBUG 0x03 # ANDROID_LOG_WARN 0x02 # ANDROID_LOG_ERROR 0x01 # ANDROID_LOG_SILENT 0x00 # NXPLOG_EXTNS_LOGLEVEL=0x03 NXPLOG_NCIHAL_LOGLEVEL=0x03 NXPLOG_NCIX_LOGLEVEL=0x03 NXPLOG_NCIR_LOGLEVEL=0x03 NXPLOG_FWDNLD_LOGLEVEL=0x03 NXPLOG_TML_LOGLEVEL=0x03 NFC_DEBUG_ENABLED=0x00 ############################################################################### # Nfc Device Node name NXP_NFC_DEV_NODE="/dev/pn544" ############################################################################### # Extension for Mifare reader enable # Disabled - 0x00 # Enabled - 0x01 MIFARE_READER_ENABLE=0x01 ############################################################################### # Firmware file type #.so file 0x01 #.bin file 0x02 NXP_FW_TYPE=0x01 ############################################################################### # System clock source selection configuration #define CLK_SRC_XTAL 1 #define CLK_SRC_PLL 2 NXP_SYS_CLK_SRC_SEL=0x01 ############################################################################### # System clock frequency selection configuration #define CLK_FREQ_13MHZ 1 #define CLK_FREQ_19_2MHZ 2 #define CLK_FREQ_24MHZ 3 #define CLK_FREQ_26MHZ 4 #define CLK_FREQ_38_4MHZ 5 #define CLK_FREQ_52MHZ 6 NXP_SYS_CLK_FREQ_SEL=0x00 ############################################################################### # The timeout value to be used for clock request acknowledgment # min value = 0x01 (1.33 ms) to max = 0x06 (2.98 ms) NXP_SYS_CLOCK_TO_CFG=0x06 ############################################################################### # NXP proprietary settings NXP_ACT_PROP_EXTN={2F, 02, 00} ############################################################################### # NFC forum profile settings NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00} ############################################################################### # NXP TVDD configurations settings # Allow NFCC to configure the external TVDD # Three configurations (0x01, 0x02 and 0x03) are supported # Only one shall be selected (hardware dependancy) # Config 1: VUP connected to VBAT # Config 2: VUP connected to external 5V # Config 3: TVDD connected to external 5V NXP_EXT_TVDD_CFG=0x02 #config1:SLALM, 3.3V for both RM and CM NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00} #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM, #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms #No dual sim NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 64, 01} #Dual SIM #NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, E4, 0A} #config3: use DCDC in CE, use Tx_Pwr_Req, SLALM, monitoring 5V from DCDC, #DCDCWaitTime=4.2ms NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A} ############################################################################### # NXP RF ALMSL configuration settings for FW VERSION = 10.01.22 # # A0, 0D, 03, 00, 40, 01 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG # A0, 0D, 06, 00, FF, 05, 04, 06, 00 RF_CLIF_CFG_BOOT SMU_PMU_REG (0x40024010) # A0, 0D, 06, 00, 35, FF, 01, FF, 02 RF_CLIF_CFG_BOOT CLIF_AGC_INPUT_REG # A0, 0D, 06, 00, 33, 07, 40, 00, 00 RF_CLIF_CFG_BOOT CLIF_AGC_CONFIG0_REG # A0, 0D, 03, 02, 40, 00 RF_CLIF_CFG_IDLE CLIF_ANA_NFCLD_REG # A0, 0D, 03, 04, 47, 02 RF_CLIF_CFG_INITIATOR CLIF_ANA_AGC_REG # A0, 0D, 06, 04, 35, F4, 01, F4, 01 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG # A0, 0D, 06, 05, 45, 80, 40, 00, 00 RF_CLIF_CFG_INITIATOR CLIF_ANA_CM_CONFIG_REG # A0, 0D, 06, 05, 35, FF, 01, FF, 02 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG # A0, 0D, 06, 05, 33, 07, 40, 00, 00 RF_CLIF_CFG_INITIATOR CLIF_AGC_CONFIG0_REG # A0, 0D, 06, 06, 44, A3, 90, 03, 00 RF_CLIF_CFG_TARGET CLIF_ANA_RX_REG # A0, 0D, 03, 06, 47, 02 RF_CLIF_CFG_TARGET CLIF_ANA_AGC_REG # A0, 0D, 06, 06, 35, FF, 03, FF, 03 RF_CLIF_CFG_TARGET CLIF_AGC_INPUT_REG # A0, 0D, 06, 06, 34, F7, 7F, 00, 10 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 06, 33, 03, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG0_REG # A0, 0D, 06, 06, 30, C8, 00, 64, 00 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 06, 2F, AF, 05, 80, 17 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 06, 03, 00, 6D, 00, 20 RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG # A0, 0D, 06, 06, 45, 80, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_ANA_CM_CONFIG_REG # A0, 0D, 03, 06, 43, 20 RF_CLIF_CFG_TARGET CLIF_ANA_PBF_CONTROL_REG # A0, 0D, 06, 06, 42, 00, 02, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 03, 06, 41, 40 RF_CLIF_CFG_TARGET CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 03, 06, 37, 08 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG # A0, 0D, 03, 06, 16, 00 RF_CLIF_CFG_TARGET CLIF_TX_UNDERSHOOT_CONFIG_REG # A0, 0D, 03, 06, 15, 00 RF_CLIF_CFG_TARGET CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 03, 06, 17, 08 RF_CLIF_CFG_TARGET CLIF_RX_CONFIG_REG # A0, 0D, 03, 06, 3F, 04 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG # A0, 0D, 03, 06, 80, 03 RF_CLIF_CFG_TARGET CLIF_SPARE_REG # A0, 0D, 03, 07, 3F, 00 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG # A0, 0D, 06, 07, 35, FF, 01, FF, 02 RF_CLIF_CFG_TARGET CLIF_AGC_INPUT_REG # A0, 0D, 03, 16, 41, 8E RF_CLIF_CFG_TECHNO_I_TXB CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 18, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 18, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG0_REG # A0, 0D, 03, 1A, 41, 8E RF_CLIF_CFG_TECHNO_I_TXF CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 1C, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 1C, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG0_REG # A0, 0D, 06, 20, 4A, 00, 00, 00, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 20, 42, 88, 10, FF, FF RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 03, 20, 41, 82 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 32, 41, 82, 07, 00, 00 RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 03, 32, 16, 00 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG # A0, 0D, 03, 32, 15, 01 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 06, 32, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 34, 2D, 24, 47, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 34, 34, 00, 00, EC, 03 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 34, 33, 0F, 01, 01, 70 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG0_REG # A0, 0D, 04, 34, 44, 21, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG # A0, 0D, 06, 38, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 38, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 04, 3A, 44, 26, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 3A, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 3A, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG0_REG # A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 3C, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 04, 3E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 3E, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 3E, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG0_REG # A0, 0D, 03, 40, 41, 8E RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 40, 42, F0, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 40, 4A, 12, 07, 00, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 04, 42, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 42, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 42, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 42, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG0_REG # A0, 0D, 04, 46, 44, 26, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 46, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 44, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 04, 4A, 44, 21, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 48, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 48, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 04, 4E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 4C, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 4C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 04, 52, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 52, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 50, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 50, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 04, 56, 44, 22, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG # A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 04, 5C, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG # A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 98, 2F, CF, 05, 80, 17 RF_CLIF_CFG_GTM_B CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 98, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_B CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 9A, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_FELICA CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 30, 44, 12, 90, 03, 00 RF_CLIF_CFG_TECHNO_T_RXF CLIF_ANA_RX_REG # A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG # A0, 0D, 03, 70, 2E, 40 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_CM_CONFIG_REG # A0, 0D, 03, 70, 45, 30 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG # A0, 0D, 06, 70, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 74, 2F, 6F, 05, 80, 12 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 74, 30, D5, 00, 40, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 74, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 78, 2F, 3F, 07, 80, C1 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 78, 30, 50, 00, 10, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 78, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 7C, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 7C, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 7C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 80, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 80, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 80, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 84, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 84, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 84, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 88, 2F, B1, 05, 80, 17 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 88, 30, A8, 00, 64, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 88, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 8E, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG # A0, 0D, 06, 94, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG # A0, 0D, 06, 10, 35, FF, 01, FF, 02 RF_CLIF_CFG_T_ACTIVE CLIF_AGC_INPUT_REG # A0, 0D, 06, 10, 34, F7, 7F, 00, 00 RF_CLIF_CFG_T_ACTIVE CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 6A, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 8C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 92, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 03, 24, 41, 40 RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 24, 42, 00, 02, FF, FF RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 03, 28, 41, 40 RF_CLIF_CFG_TECHNO_T_TXB CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 03, 8A, 41, 40 RF_CLIF_CFG_BR_212_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 03, 90, 41, 40 RF_CLIF_CFG_BR_424_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 03, 08, 40, 10 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_NFCLD_REG # A0, 0D, 06, 08, 45, C0, 82, 00, 00 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_CM_CONFIG_REG # A0, 0D, 06, 0A, 45, 80, 40, 00, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CM_CONFIG_REG # A0, 0D, 06, 0A, 30, C8, 00, 64, 00 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 0A, 2F, AF, 05, 80, 17 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 0A, 34, 26, 65, E5, 03 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 0A, 33, 0F, 01, 00, 70 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG0_REG # A0, 0D, 03, 0A, 40, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_NFCLD_REG # # *** ALMSL FW VERSION = 10.01.22 *** NXP_RF_CONF_BLK_1={ 20, 02, F7, 20, A0, 0D, 03, 00, 40, 01, A0, 0D, 06, 00, FF, 05, 04, 06, 00, A0, 0D, 06, 00, 35, FF, 01, FF, 02, A0, 0D, 06, 00, 33, 07, 40, 00, 00, A0, 0D, 03, 02, 40, 00, A0, 0D, 03, 04, 47, 02, A0, 0D, 06, 04, 35, F4, 01, F4, 01, A0, 0D, 06, 05, 45, 80, 40, 00, 00, A0, 0D, 06, 05, 35, FF, 01, FF, 02, A0, 0D, 06, 05, 33, 07, 40, 00, 00, A0, 0D, 06, 06, 44, A3, 90, 03, 00, A0, 0D, 03, 06, 47, 02, A0, 0D, 06, 06, 35, FF, 03, FF, 03, A0, 0D, 06, 06, 34, F7, 7F, 00, 10, A0, 0D, 06, 06, 33, 03, 40, 00, 00, A0, 0D, 06, 06, 30, C8, 00, 64, 00, A0, 0D, 06, 06, 2F, AF, 05, 80, 17, A0, 0D, 06, 06, 03, 00, 73, 00, 20, A0, 0D, 06, 06, 45, 80, 40, 00, 00, A0, 0D, 03, 06, 43, 20, A0, 0D, 06, 06, 42, 00, 02, F2, F2, A0, 0D, 03, 06, 41, 40, A0, 0D, 03, 06, 37, 08, A0, 0D, 03, 06, 16, 00, A0, 0D, 03, 06, 15, 00, A0, 0D, 03, 06, 17, 08, A0, 0D, 03, 06, 3F, 04, A0, 0D, 03, 06, 80, 03, A0, 0D, 03, 07, 3F, 00, A0, 0D, 06, 07, 35, FF, 01, FF, 02, A0, 0D, 03, 16, 41, 8E, A0, 0D, 06, 18, 34, 00, 00, E1, 03 } NXP_RF_CONF_BLK_2={ 20, 02, FA, 1E, A0, 0D, 06, 18, 33, 0F, 83, 00, 00, A0, 0D, 03, 1A, 41, 8E, A0, 0D, 06, 1C, 34, 00, 00, E1, 03, A0, 0D, 06, 1C, 33, 0F, 83, 00, 00, A0, 0D, 06, 20, 4A, 00, 00, 00, 00, A0, 0D, 06, 20, 42, 88, 10, FF, FF, A0, 0D, 03, 20, 41, 82, A0, 0D, 06, 32, 42, F8, 10, FF, FF, A0, 0D, 06, 32, 41, 82, 07, 00, 00, A0, 0D, 03, 32, 16, 00, A0, 0D, 03, 32, 15, 01, A0, 0D, 06, 32, 4A, 33, 07, 00, 08, A0, 0D, 06, 34, 2D, 24, 47, 0C, 00, A0, 0D, 06, 34, 34, 00, 00, EC, 03, A0, 0D, 06, 34, 33, 0F, 01, 01, 70, A0, 0D, 04, 34, 44, 22, 00, A0, 0D, 06, 38, 4A, 33, 07, 00, 08, A0, 0D, 06, 38, 42, 68, 10, FF, FF, A0, 0D, 04, 3A, 44, 26, 00, A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00, A0, 0D, 06, 3A, 34, 00, 00, E1, 03, A0, 0D, 06, 3A, 33, 0B, 83, 00, 00, A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B, A0, 0D, 06, 3C, 42, 68, 10, FF, FF, A0, 0D, 04, 3E, 44, 26, 00, A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00, A0, 0D, 06, 3E, 34, 00, 00, E1, 03, A0, 0D, 06, 3E, 33, 0B, 83, 00, 00, A0, 0D, 03, 40, 41, 8E, A0, 0D, 06, 40, 42, F0, 10, FF, FF } NXP_RF_CONF_BLK_3={ 20, 02, F8, 1D, A0, 0D, 06, 40, 4A, 12, 07, 00, 00, A0, 0D, 04, 42, 44, 26, 00, A0, 0D, 06, 42, 2D, 15, 47, 0D, 00, A0, 0D, 06, 42, 34, 00, 00, E1, 03, A0, 0D, 06, 42, 33, 0B, 83, 00, 00, A0, 0D, 04, 46, 44, 26, 00, A0, 0D, 06, 46, 2D, 15, 25, 0D, 00, A0, 0D, 06, 44, 4A, 21, 07, 00, 07, A0, 0D, 06, 44, 42, 88, 10, FF, FF, A0, 0D, 04, 4A, 44, 21, 00, A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00, A0, 0D, 06, 48, 4A, 21, 07, 00, 07, A0, 0D, 06, 48, 42, 88, 10, FF, FF, A0, 0D, 04, 4E, 44, 26, 00, A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00, A0, 0D, 06, 4C, 4A, 21, 07, 00, 07, A0, 0D, 06, 4C, 42, 88, 10, FF, FF, A0, 0D, 04, 52, 44, 26, 00, A0, 0D, 06, 52, 2D, 15, 25, 0D, 00, A0, 0D, 06, 50, 42, 90, 10, FF, FF, A0, 0D, 06, 50, 4A, 21, 07, 00, 07, A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00, A0, 0D, 04, 56, 44, 22, 00, A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00, A0, 0D, 04, 5C, 44, 26, 00, A0, 0D, 06, 54, 42, 88, 10, FF, FF, A0, 0D, 06, 5A, 42, 90, 10, FF, FF, A0, 0D, 06, 98, 2F, CF, 05, 80, 17, A0, 0D, 06, 98, 42, 00, 02, F2, F2 } NXP_RF_CONF_BLK_4={ 20, 02, F7, 1C, A0, 0D, 06, 9A, 42, 00, 02, F2, F2, A0, 0D, 06, 30, 44, 12, 90, 03, 00, A0, 0D, 06, 6C, 44, A3, 90, 03, 00, A0, 0D, 03, 70, 2E, 40, A0, 0D, 03, 70, 45, 30, A0, 0D, 06, 70, 44, A3, 90, 03, 00, A0, 0D, 06, 74, 2F, 6F, 05, 80, 12, A0, 0D, 06, 74, 30, D5, 00, 40, 00, A0, 0D, 06, 74, 44, A3, 90, 03, 00, A0, 0D, 06, 78, 2F, 3F, 07, 80, C1, A0, 0D, 06, 78, 30, 50, 00, 10, 00, A0, 0D, 06, 78, 44, A3, 90, 03, 00, A0, 0D, 06, 7C, 2F, CF, 05, 80, 17, A0, 0D, 06, 7C, 30, C8, 00, 64, 00, A0, 0D, 06, 7C, 44, A3, 90, 03, 00, A0, 0D, 06, 80, 2F, CF, 05, 80, 17, A0, 0D, 06, 80, 30, C8, 00, 64, 00, A0, 0D, 06, 80, 44, A3, 90, 03, 00, A0, 0D, 06, 84, 2F, CF, 05, 80, 17, A0, 0D, 06, 84, 30, C8, 00, 64, 00, A0, 0D, 06, 84, 44, A3, 90, 03, 00, A0, 0D, 06, 88, 2F, B1, 05, 80, 17, A0, 0D, 06, 88, 30, A8, 00, 64, 00, A0, 0D, 06, 88, 44, A3, 90, 03, 00, A0, 0D, 06, 8E, 44, 12, 90, 03, 00, A0, 0D, 06, 94, 44, 12, 90, 03, 00, A0, 0D, 06, 10, 35, FF, 01, FF, 02, A0, 0D, 06, 10, 34, F7, 7F, 00, 00 } NXP_RF_CONF_BLK_5={ 20, 02, 7F, 10, A0, 0D, 06, 6A, 42, F8, 10, FF, FF, A0, 0D, 06, 8C, 42, 88, 10, FF, FF, A0, 0D, 06, 92, 42, 90, 10, FF, FF, A0, 0D, 03, 24, 41, 40, A0, 0D, 06, 24, 42, 00, 02, F2, F2, A0, 0D, 03, 28, 41, 40, A0, 0D, 03, 8A, 41, 40, A0, 0D, 03, 90, 41, 40, A0, 0D, 03, 08, 40, 10, A0, 0D, 06, 08, 45, C0, 82, 00, 00, A0, 0D, 06, 0A, 45, 80, 40, 00, 00, A0, 0D, 06, 0A, 30, C8, 00, 64, 00, A0, 0D, 06, 0A, 2F, AF, 05, 80, 17, A0, 0D, 06, 0A, 34, 26, 65, E5, 03, A0, 0D, 06, 0A, 33, 0F, 01, 00, 70, A0, 0D, 03, 0A, 40, 00 } ############################################################################### # Core configuration extensions # It includes # A002 - Disable/Enable Clock Request # A009 - Time-out before standby # A012 - NFCEE interface 2 configuration # A040 - Low Power Card Detector Enable # A041 - Low Power Card Detector Threshold # A042 - Low Power Card Detector Sampling # A043 - Low Power Card Detector Hybrid # A05E - Send RID automatically in Jewel Reader mode # A061 - Retry after LPCD # A096 - Notification for all AIDs in Card emulation mode # A0DD - Number of retry for DWP # A0EC - Disable/Enable SWP1 interface # A0ED - Disable/Enable SWP2 interface # A0F2 - SWP_SVDD_ON_CFG # CLIF_ANA_CLK_MAN_REG Phone ON A01D # CLIF_ANA_CLK_MAN_REG Phone OFF A01E NXP_CORE_CONF_EXTN={20, 02, 75, 13, A0, 02, 01, 01, A0, 09, 02, 90, 01, A0, 12, 01, 00, A0, 40, 01, 01, A0, 41, 01, 05, A0, 42, 01, 0F, A0, 43, 01, 03, A0, 5E, 01, 01, A0, 61, 01, 53, A0, 68, 01, 01, A0, 96, 01, 01, A0, DD, 01, 2D, A0, EC, 01, 01, A0, ED, 01, 00, A0, F2, 01, 00, A0, CA, 07, 02, 00, 1F, 01, 1F, 0F, 20, A0, 47, 02, 00, 27, A0, 1D, 11, 57, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00, A0, 1E, 11, 18, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00 } ############################################################################### # Core configuration RF Field notification filter # Disabled - 0x00 # Enabled - 0x01 NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00} ############################################################################### # I2C fragmentation # Disabled - 0x00 # Enabled - 0x01 NXP_I2C_FRAGMENTATION_ENABLED=0x00 ############################################################################### # Core configuration settings # It includes # 18 - Poll Mode NFC-F: PF_BIT_RATE # 21 - Poll Mode ISO-DEP: PI_BIT_RATE # 28 - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED # 30 - Lis. Mode NFC-A: LA_BIT_FRAME_SDD # 31 - Lis. Mode NFC-A: LA_PLATFORM_CONFIG # 50 - Lis. Mode NFC-F: LF_PROTOCOL_TYPE # 54 - Lis. Mode NFC-F: LF_CON_BITR_F # 5B - Lis. Mode ISO-DEP: LI_BIT_RATE # 60 - Lis. Mode NFC-DEP: LN_WT # 80 - Other Param.: RF_FIELD_INFO # 81 - Other Param.: RF_NFCEE_ACTION # 82 - Other Param.: NFCDEP_OP NXP_CORE_CONF={20, 02, 2A, 0E, 18, 01, 01, 21, 01, 00, 28, 01, 00, 30, 01, 04, 31, 01, 00, 33, 00, 50, 01, 02, 54, 01, 06, 5B, 01, 00, 60, 01, 0E, 80, 01, 01, 81, 01, 01, 82, 01, 0E, 32, 01, 60 } ############################################################################### #Enable SWP full power mode when phone is power off NXP_SWP_FULL_PWR_ON=0x00 ############################################################################### #Set the default Felica T3T System Code OffHost route Location : # host 0x00 # UICC 0x02 # UICC2 0x03 DEFAULT_SYS_CODE_ROUTE=0x02 ############################################################################### #Set the Felica T3T System Code Power state : #This settings will be used when application does not set this parameter # bit pos 0 = Switch On # bit pos 1 = Switch Off # bit pos 2 = Battery Off # bit pos 3 = Screen On lock # bit pos 4 = Screen off unlock # bit pos 5 = Screen Off lock DEFAULT_SYS_CODE_PWR_STATE=0x19 ############################################################################### # AID Matching platform options # AID_MATCHING_L 0x01 # AID_MATCHING_K 0x02 AID_MATCHING_PLATFORM=0x01 ############################################################################### #CHINA_TIANJIN_RF_SETTING #Enable 0x01 #Disable 0x00 NXP_CHINA_TIANJIN_RF_ENABLED=0x01 ############################################################################### #SWP_SWITCH_TIMEOUT_SETTING # Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60]. # Timeout in milliseconds, for example # No Timeout 0x00 # 10 millisecond timeout 0x0A NXP_SWP_SWITCH_TIMEOUT=0x0A ############################################################################### # Vendor Specific Proprietary Protocol & Discovery Configuration # Set to 0xFF if unsupported # byte[0] NCI_PROTOCOL_18092_ACTIVE # byte[1] NCI_PROTOCOL_B_PRIME # byte[2] NCI_PROTOCOL_DUAL # byte[3] NCI_PROTOCOL_15693 # byte[4] NCI_PROTOCOL_KOVIO # byte[5] NCI_PROTOCOL_MIFARE # byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO # byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME # byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME NFA_PROPRIETARY_CFG={05, FF, FF, 06, 81, 80, 70, FF, FF} ############################################################################### # Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1. # 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm # 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block # 2 NFA_RW_PRES_CHK_RESET; Deactivate to Sleep, then re-activate # 3 NFA_RW_PRES_CHK_RB_CH0; Type-4 tag protocol's ReadBinary command on channel 0 # 4 NFA_RW_PRES_CHK_RB_CH3; Type-4 tag protocol's ReadBinary command on channel 3 PRESENCE_CHECK_ALGORITHM=1 ################################################################################ # Restriction of Type A UICC baud rate # Default supported - 0x00 # 212kbps maximum supported - 0x01 # 424kbps maximum supported - 0x02 # 848kbps maximum supported - 0x03 NXP_TYPEA_UICC_BAUD_RATE=0x00 ################################################################################ # Restriction of Type B UICC baud rate # Default supported - 0x00 # 212kbps maximum supported - 0x01 # 424kbps maximum supported - 0x02 # 848kbps maximum supported - 0x03 NXP_TYPEB_UICC_BAUD_RATE=0x00