diff --git a/configs/libnfc-brcm.conf b/configs/libnfc-brcm.conf index b762f39..f65cb6d 100644 --- a/configs/libnfc-brcm.conf +++ b/configs/libnfc-brcm.conf @@ -1,4 +1,4 @@ -###################### Start of libnfc-brcm.conf ####################### +###################### Start of libnfc-common.conf ####################### ############################################################################### # Application options @@ -305,6 +305,7 @@ MAX_RF_DATA_CREDITS=1 # array[1] = 0xC8 is PREINIT_DSP_CFG #PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04} + ############################################################################### # Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1. # 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm @@ -326,8 +327,8 @@ PRESENCE_CHECK_ALGORITHM=1 # NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */ # NFA_TECHNOLOGY_MASK_B 0x02 /* NFC Technology B */ # NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */ -# NFA_TECHNOLOGY_MASK_ISO15693 0x08 /* Proprietary Technology */ -# NFA_TECHNOLOGY_MASK_KOVIO 0x20 /* Proprietary Technology */ +# NFA_TECHNOLOGY_MASK_ISO15693 0x08 /* Proprietary Technology */ +# NFA_TECHNOLOGY_MASK_KOVIO 0x20 /* Proprietary Technology */ # NFA_TECHNOLOGY_MASK_A_ACTIVE 0x40 /* NFC Technology A active mode */ # NFA_TECHNOLOGY_MASK_F_ACTIVE 0x80 /* NFC Technology F active mode */ POLLING_TECH_MASK=0xEF @@ -339,8 +340,8 @@ POLLING_TECH_MASK=0xEF # NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE # # Notable bits: -# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */ -# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */ +# NFA_TECHNOLOGY_MASK_A 0x01 /* NFC Technology A */ +# NFA_TECHNOLOGY_MASK_F 0x04 /* NFC Technology F */ # NFA_TECHNOLOGY_MASK_A_ACTIVE 0x40 /* NFC Technology A active mode */ # NFA_TECHNOLOGY_MASK_F_ACTIVE 0x80 /* NFC Technology F active mode */ P2P_LISTEN_TECH_MASK=0xC5 @@ -394,8 +395,8 @@ DEFAULT_OFFHOST_ROUTE=0x02 # byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME NFA_PROPRIETARY_CFG={05:FF:FF:06:81:80:70:FF:FF} -############################################################################### +################################################################################# # Bail out mode # If set to 1, NFCC is using bail out mode for either Type A or Type B poll. NFA_POLL_BAIL_OUT_MODE=0x01 - +################################################################################# diff --git a/configs/libnfc-nxp.conf b/configs/libnfc-nxp.conf index e9d140c..c9dbb0d 100644 --- a/configs/libnfc-nxp.conf +++ b/configs/libnfc-nxp.conf @@ -1,6 +1,6 @@ ############################################################################### ## Modified by Motorola Mobility LLC -## Version : 3.8 (2017/02/20) +## Version : 4.2 (2017/05/23) ## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn548) ## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn548) @@ -46,7 +46,7 @@ NXP_FW_NAME="libpn548ad_fw.so" #define CLK_SRC_XTAL 1 #define CLK_SRC_PLL 2 -NXP_SYS_CLK_SRC_SEL=0x02 +NXP_SYS_CLK_SRC_SEL=0x01 ############################################################################### # System clock frequency selection configuration @@ -57,7 +57,7 @@ NXP_SYS_CLK_SRC_SEL=0x02 #define CLK_FREQ_38_4MHZ 5 #define CLK_FREQ_52MHZ 6 -NXP_SYS_CLK_FREQ_SEL=0x02 +NXP_SYS_CLK_FREQ_SEL=0x00 ############################################################################### # The timeout value to be used for clock request acknowledgment @@ -111,17 +111,15 @@ NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A} ############################################################################### -# NXP RF ALMSL configuration settings for FW VERSION = 10.01.1B +# NXP RF ALMSL configuration settings for FW VERSION = 10.01.22 # # A0, 0D, 03, 00, 40, 01 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG # A0, 0D, 06, 00, FF, 05, 04, 06, 00 RF_CLIF_CFG_BOOT SMU_PMU_REG (0x40024010) # A0, 0D, 06, 00, 35, FF, 01, FF, 02 RF_CLIF_CFG_BOOT CLIF_AGC_INPUT_REG # A0, 0D, 06, 00, 33, 07, 40, 00, 00 RF_CLIF_CFG_BOOT CLIF_AGC_CONFIG0_REG # A0, 0D, 03, 02, 40, 00 RF_CLIF_CFG_IDLE CLIF_ANA_NFCLD_REG -# A0, 0D, 03, 04, 43, 20 RF_CLIF_CFG_INITIATOR CLIF_ANA_PBF_CONTROL_REG # A0, 0D, 03, 04, 47, 02 RF_CLIF_CFG_INITIATOR CLIF_ANA_AGC_REG # A0, 0D, 06, 04, 35, F4, 01, F4, 01 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG -# A0, 0D, 06, 04, FF, 05, 00, 00, 00 RF_CLIF_CFG_INITIATOR SMU_PMU_REG (0x40024010) # A0, 0D, 06, 05, 45, 80, 40, 00, 00 RF_CLIF_CFG_INITIATOR CLIF_ANA_CM_CONFIG_REG # A0, 0D, 06, 05, 35, FF, 01, FF, 02 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG # A0, 0D, 06, 05, 33, 07, 40, 00, 00 RF_CLIF_CFG_INITIATOR CLIF_AGC_CONFIG0_REG @@ -133,34 +131,31 @@ NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A} # A0, 0D, 06, 06, 30, C8, 00, 64, 00 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 06, 2F, AF, 05, 80, 17 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 06, 03, 00, 6D, 00, 20 RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG +# A0, 0D, 06, 06, 45, 80, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_ANA_CM_CONFIG_REG # A0, 0D, 03, 06, 43, 20 RF_CLIF_CFG_TARGET CLIF_ANA_PBF_CONTROL_REG # A0, 0D, 06, 06, 42, 00, 02, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 03, 06, 41, 40 RF_CLIF_CFG_TARGET CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 03, 06, 37, 08 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG # A0, 0D, 03, 06, 16, 00 RF_CLIF_CFG_TARGET CLIF_TX_UNDERSHOOT_CONFIG_REG # A0, 0D, 03, 06, 15, 00 RF_CLIF_CFG_TARGET CLIF_TX_OVERSHOOT_CONFIG_REG +# A0, 0D, 03, 06, 17, 08 RF_CLIF_CFG_TARGET CLIF_RX_CONFIG_REG # A0, 0D, 03, 06, 3F, 04 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG # A0, 0D, 03, 06, 80, 03 RF_CLIF_CFG_TARGET CLIF_SPARE_REG -# A0, 0D, 06, 06, FF, 05, 00, 00, 00 RF_CLIF_CFG_TARGET SMU_PMU_REG (0x40024010) # A0, 0D, 03, 07, 3F, 00 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG # A0, 0D, 06, 07, 35, FF, 01, FF, 02 RF_CLIF_CFG_TARGET CLIF_AGC_INPUT_REG -# A0, 0D, 06, 07, 33, 07, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG0_REG +# A0, 0D, 03, 16, 41, 8E RF_CLIF_CFG_TECHNO_I_TXB CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 18, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 18, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG0_REG +# A0, 0D, 03, 1A, 41, 8E RF_CLIF_CFG_TECHNO_I_TXF CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 1C, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 1C, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG0_REG # A0, 0D, 06, 20, 4A, 00, 00, 00, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 20, 42, 88, 10, FF, FF RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 03, 20, 16, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 20, 15, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_OVERSHOOT_CONFIG_REG -# A0, 0D, 04, 22, 44, 22, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_ANA_RX_REG -# A0, 0D, 06, 22, 2D, 50, 44, 0C, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_SIGPRO_RM_CONFIG1_REG -# A0, 0D, 04, 32, 03, 40, 3D RF_CLIF_CFG_BR_106_I_TXA CLIF_TRANSCEIVE_CONTROL_REG +# A0, 0D, 03, 20, 41, 82 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG +# A0, 0D, 06, 32, 41, 82, 07, 00, 00 RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 03, 32, 16, 00 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG # A0, 0D, 03, 32, 15, 01 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG -# A0, 0D, 03, 32, 0D, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_DATA_MOD_REG -# A0, 0D, 03, 32, 14, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_SYMBOL23_MOD_REG # A0, 0D, 06, 32, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 34, 2D, 24, 47, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 34, 34, 00, 00, EC, 03 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG1_REG @@ -168,26 +163,19 @@ NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A} # A0, 0D, 04, 34, 44, 21, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG # A0, 0D, 06, 38, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 38, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 03, 38, 16, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 38, 15, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 04, 3A, 44, 26, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 3A, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 3A, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG0_REG # A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 3C, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 03, 3C, 16, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 3C, 15, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 04, 3E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 3E, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 3E, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG0_REG +# A0, 0D, 03, 40, 41, 8E RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 40, 42, F0, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 03, 40, 0D, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_DATA_MOD_REG -# A0, 0D, 03, 40, 14, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_SYMBOL23_MOD_REG # A0, 0D, 06, 40, 4A, 12, 07, 00, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG -# A0, 0D, 03, 40, 16, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 40, 15, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 04, 42, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_ANA_RX_REG # A0, 0D, 06, 42, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 42, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG1_REG @@ -196,47 +184,29 @@ NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A} # A0, 0D, 06, 46, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 44, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 03, 44, 16, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 44, 15, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 04, 4A, 44, 21, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 48, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 48, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 03, 48, 16, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 48, 15, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 04, 4E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 4C, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 4C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 03, 4C, 16, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 4C, 15, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 04, 52, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 52, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 06, 50, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 50, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG -# A0, 0D, 03, 50, 16, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 50, 15, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 04, 56, 44, 22, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG # A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG # A0, 0D, 04, 5C, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG # A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 06, 54, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG -# A0, 0D, 03, 54, 16, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 54, 15, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 06, 5A, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG -# A0, 0D, 03, 5A, 16, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 5A, 15, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 06, 98, 2F, CF, 05, 80, 17 RF_CLIF_CFG_GTM_B CLIF_SIGPRO_ADCBCM_CONFIG_REG # A0, 0D, 06, 98, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_B CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 9A, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_FELICA CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 06, 30, 44, 12, 90, 03, 00 RF_CLIF_CFG_TECHNO_T_RXF CLIF_ANA_RX_REG # A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG -# A0, 0D, 06, 6C, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG -# A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG -# A0, 0D, 06, 70, 2F, 8F, 05, 80, 12 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG -# A0, 0D, 06, 70, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 03, 70, 2E, 40 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_CM_CONFIG_REG # A0, 0D, 03, 70, 45, 30 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG # A0, 0D, 06, 70, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_RX_REG @@ -260,21 +230,11 @@ NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A} # A0, 0D, 06, 88, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_ANA_RX_REG # A0, 0D, 06, 8E, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG # A0, 0D, 06, 94, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG -# A0, 0D, 03, 10, 43, 20 RF_CLIF_CFG_T_ACTIVE CLIF_ANA_PBF_CONTROL_REG # A0, 0D, 06, 10, 35, FF, 01, FF, 02 RF_CLIF_CFG_T_ACTIVE CLIF_AGC_INPUT_REG # A0, 0D, 06, 10, 34, F7, 7F, 00, 00 RF_CLIF_CFG_T_ACTIVE CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 6A, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 03, 6A, 16, 00 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 6A, 15, 01 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_OVERSHOOT_CONFIG_REG -# A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_SHAPE_CONTROL_REG # A0, 0D, 06, 8C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 06, 8C, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG -# A0, 0D, 03, 8C, 16, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 8C, 15, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 06, 92, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG -# A0, 0D, 06, 92, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG -# A0, 0D, 03, 92, 16, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG -# A0, 0D, 03, 92, 15, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG # A0, 0D, 03, 24, 41, 40 RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 06, 24, 42, 00, 02, FF, FF RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG # A0, 0D, 03, 28, 41, 40 RF_CLIF_CFG_TECHNO_T_TXB CLIF_ANA_TX_CLK_CONTROL_REG @@ -282,70 +242,63 @@ NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A} # A0, 0D, 03, 90, 41, 40 RF_CLIF_CFG_BR_424_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG # A0, 0D, 03, 08, 40, 10 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_NFCLD_REG # A0, 0D, 06, 08, 45, C0, 82, 00, 00 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_CM_CONFIG_REG -# A0, 0D, 06, 0A, 44, A3, 90, 03, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_RX_REG # A0, 0D, 06, 0A, 45, 80, 40, 00, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CM_CONFIG_REG # A0, 0D, 06, 0A, 30, C8, 00, 64, 00 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG # A0, 0D, 06, 0A, 2F, AF, 05, 80, 17 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_CONFIG_REG -# A0, 0D, 03, 0A, 48, 10 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG # A0, 0D, 06, 0A, 34, 26, 65, E5, 03 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG1_REG # A0, 0D, 06, 0A, 33, 0F, 01, 00, 70 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG0_REG # A0, 0D, 03, 0A, 40, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_NFCLD_REG # -# *** ALMSL FW VERSION = 10.01.1B *** +# *** ALMSL FW VERSION = 10.01.22 *** NXP_RF_CONF_BLK_1={ - 20, 02, FA, 20, - A0, 0D, 03, 00, 40, 03, + 20, 02, F7, 20, + A0, 0D, 03, 00, 40, 01, A0, 0D, 06, 00, FF, 05, 04, 06, 00, - A0, 0D, 06, 00, 35, 00, 00, FF, 02, + A0, 0D, 06, 00, 35, FF, 01, FF, 02, A0, 0D, 06, 00, 33, 07, 40, 00, 00, A0, 0D, 03, 02, 40, 00, - A0, 0D, 03, 04, 43, 20, A0, 0D, 03, 04, 47, 02, - A0, 0D, 06, 04, 35, F4, 02, F4, 02, - A0, 0D, 06, 04, FF, 05, 00, 00, 00, + A0, 0D, 06, 04, 35, F4, 01, F4, 01, A0, 0D, 06, 05, 45, 80, 40, 00, 00, A0, 0D, 06, 05, 35, FF, 01, FF, 02, A0, 0D, 06, 05, 33, 07, 40, 00, 00, A0, 0D, 06, 06, 44, A3, 90, 03, 00, A0, 0D, 03, 06, 47, 02, - A0, 0D, 06, 06, 35, 00, 01, 00, 02, + A0, 0D, 06, 06, 35, FF, 03, FF, 03, A0, 0D, 06, 06, 34, F7, 7F, 00, 10, A0, 0D, 06, 06, 33, 03, 40, 00, 00, - A0, 0D, 06, 06, 30, B0, 00, 10, 00, + A0, 0D, 06, 06, 30, C8, 00, 64, 00, A0, 0D, 06, 06, 2F, AF, 05, 80, 17, - A0, 0D, 06, 06, 03, 00, 72, 00, 20, + A0, 0D, 06, 06, 03, 00, 73, 00, 20, + A0, 0D, 06, 06, 45, 80, 40, 00, 00, A0, 0D, 03, 06, 43, 20, - A0, 0D, 06, 06, 42, 00, 03, F3, F3, + A0, 0D, 06, 06, 42, 00, 02, F2, F2, A0, 0D, 03, 06, 41, 40, A0, 0D, 03, 06, 37, 08, A0, 0D, 03, 06, 16, 00, A0, 0D, 03, 06, 15, 00, + A0, 0D, 03, 06, 17, 08, A0, 0D, 03, 06, 3F, 04, A0, 0D, 03, 06, 80, 03, - A0, 0D, 06, 06, FF, 05, 00, 00, 00, A0, 0D, 03, 07, 3F, 00, A0, 0D, 06, 07, 35, FF, 01, FF, 02, - A0, 0D, 06, 07, 33, 07, 40, 00, 00 + A0, 0D, 03, 16, 41, 8E, + A0, 0D, 06, 18, 34, 00, 00, E1, 03 } NXP_RF_CONF_BLK_2={ - 20, 02, F8, 1F, - A0, 0D, 06, 18, 34, 00, 00, E1, 03, + 20, 02, FA, 1E, A0, 0D, 06, 18, 33, 0F, 83, 00, 00, + A0, 0D, 03, 1A, 41, 8E, A0, 0D, 06, 1C, 34, 00, 00, E1, 03, A0, 0D, 06, 1C, 33, 0F, 83, 00, 00, A0, 0D, 06, 20, 4A, 00, 00, 00, 00, A0, 0D, 06, 20, 42, 88, 10, FF, FF, - A0, 0D, 03, 20, 16, 00, - A0, 0D, 03, 20, 15, 00, - A0, 0D, 04, 22, 44, 22, 00, - A0, 0D, 06, 22, 2D, 50, 44, 0C, 00, - A0, 0D, 04, 32, 03, 40, 3D, + A0, 0D, 03, 20, 41, 82, A0, 0D, 06, 32, 42, F8, 10, FF, FF, + A0, 0D, 06, 32, 41, 82, 07, 00, 00, A0, 0D, 03, 32, 16, 00, A0, 0D, 03, 32, 15, 01, - A0, 0D, 03, 32, 0D, 22, - A0, 0D, 03, 32, 14, 22, A0, 0D, 06, 32, 4A, 33, 07, 00, 08, A0, 0D, 06, 34, 2D, 24, 47, 0C, 00, A0, 0D, 06, 34, 34, 00, 00, EC, 03, @@ -353,30 +306,24 @@ NXP_RF_CONF_BLK_2={ A0, 0D, 04, 34, 44, 22, 00, A0, 0D, 06, 38, 4A, 33, 07, 00, 08, A0, 0D, 06, 38, 42, 68, 10, FF, FF, - A0, 0D, 03, 38, 16, 00, - A0, 0D, 03, 38, 15, 00, A0, 0D, 04, 3A, 44, 26, 00, A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00, A0, 0D, 06, 3A, 34, 00, 00, E1, 03, A0, 0D, 06, 3A, 33, 0B, 83, 00, 00, A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B, - A0, 0D, 06, 3C, 42, 68, 10, FF, FF -} + A0, 0D, 06, 3C, 42, 68, 10, FF, FF, -NXP_RF_CONF_BLK_3={ - 20, 02, F9, 20, - A0, 0D, 03, 3C, 16, 00, - A0, 0D, 03, 3C, 15, 00, A0, 0D, 04, 3E, 44, 26, 00, A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00, A0, 0D, 06, 3E, 34, 00, 00, E1, 03, A0, 0D, 06, 3E, 33, 0B, 83, 00, 00, - A0, 0D, 06, 40, 42, F0, 10, FF, FF, - A0, 0D, 03, 40, 0D, 02, - A0, 0D, 03, 40, 14, 02, + A0, 0D, 03, 40, 41, 8E, + A0, 0D, 06, 40, 42, F0, 10, FF, FF +} + +NXP_RF_CONF_BLK_3={ + 20, 02, F8, 1D, A0, 0D, 06, 40, 4A, 12, 07, 00, 00, - A0, 0D, 03, 40, 16, 00, - A0, 0D, 03, 40, 15, 00, A0, 0D, 04, 42, 44, 26, 00, A0, 0D, 06, 42, 2D, 15, 47, 0D, 00, A0, 0D, 06, 42, 34, 00, 00, E1, 03, @@ -385,57 +332,36 @@ NXP_RF_CONF_BLK_3={ A0, 0D, 06, 46, 2D, 15, 25, 0D, 00, A0, 0D, 06, 44, 4A, 21, 07, 00, 07, A0, 0D, 06, 44, 42, 88, 10, FF, FF, - A0, 0D, 03, 44, 16, 00, - A0, 0D, 03, 44, 15, 00, A0, 0D, 04, 4A, 44, 21, 00, A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00, A0, 0D, 06, 48, 4A, 21, 07, 00, 07, A0, 0D, 06, 48, 42, 88, 10, FF, FF, - A0, 0D, 03, 48, 16, 00, - A0, 0D, 03, 48, 15, 00, A0, 0D, 04, 4E, 44, 26, 00, A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00, A0, 0D, 06, 4C, 4A, 21, 07, 00, 07, - A0, 0D, 06, 4C, 42, 88, 10, FF, FF -} + A0, 0D, 06, 4C, 42, 88, 10, FF, FF, -NXP_RF_CONF_BLK_4={ - 20, 02, F4, 1F, - A0, 0D, 03, 4C, 16, 00, - A0, 0D, 03, 4C, 15, 00, A0, 0D, 04, 52, 44, 26, 00, A0, 0D, 06, 52, 2D, 15, 25, 0D, 00, A0, 0D, 06, 50, 42, 90, 10, FF, FF, A0, 0D, 06, 50, 4A, 21, 07, 00, 07, - A0, 0D, 03, 50, 16, 00, - A0, 0D, 03, 50, 15, 00, A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00, A0, 0D, 04, 56, 44, 22, 00, A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00, A0, 0D, 04, 5C, 44, 26, 00, A0, 0D, 06, 54, 42, 88, 10, FF, FF, - A0, 0D, 06, 54, 4A, 33, 07, 01, 07, - A0, 0D, 03, 54, 16, 00, - A0, 0D, 03, 54, 15, 00, A0, 0D, 06, 5A, 42, 90, 10, FF, FF, - A0, 0D, 06, 5A, 4A, 31, 07, 01, 07, - A0, 0D, 03, 5A, 16, 00, - A0, 0D, 03, 5A, 15, 00, A0, 0D, 06, 98, 2F, CF, 05, 80, 17, - A0, 0D, 06, 98, 42, 00, 03, F3, F3, - A0, 0D, 06, 9A, 42, 00, 03, F3, F3, + A0, 0D, 06, 98, 42, 00, 02, F2, F2 +} +NXP_RF_CONF_BLK_4={ + 20, 02, F7, 1C, + A0, 0D, 06, 9A, 42, 00, 02, F2, F2, A0, 0D, 06, 30, 44, 12, 90, 03, 00, A0, 0D, 06, 6C, 44, A3, 90, 03, 00, - A0, 0D, 06, 6C, 30, CF, 00, 08, 00, - A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C, - A0, 0D, 06, 70, 2F, 8F, 05, 80, 12, - A0, 0D, 06, 70, 30, CF, 00, 08, 00, A0, 0D, 03, 70, 2E, 40, - A0, 0D, 03, 70, 45, 30 -} + A0, 0D, 03, 70, 45, 30, -NXP_RF_CONF_BLK_5={ - 20, 02, F4, 1C, A0, 0D, 06, 70, 44, A3, 90, 03, 00, A0, 0D, 06, 74, 2F, 6F, 05, 80, 12, A0, 0D, 06, 74, 30, D5, 00, 40, 00, @@ -444,7 +370,7 @@ NXP_RF_CONF_BLK_5={ A0, 0D, 06, 78, 30, 50, 00, 10, 00, A0, 0D, 06, 78, 44, A3, 90, 03, 00, A0, 0D, 06, 7C, 2F, CF, 05, 80, 17, - A0, 0D, 06, 7C, 30, B0, 00, 10, 00, + A0, 0D, 06, 7C, 30, C8, 00, 64, 00, A0, 0D, 06, 7C, 44, A3, 90, 03, 00, A0, 0D, 06, 80, 2F, CF, 05, 80, 17, A0, 0D, 06, 80, 30, C8, 00, 64, 00, @@ -457,37 +383,25 @@ NXP_RF_CONF_BLK_5={ A0, 0D, 06, 88, 44, A3, 90, 03, 00, A0, 0D, 06, 8E, 44, 12, 90, 03, 00, A0, 0D, 06, 94, 44, 12, 90, 03, 00, - A0, 0D, 03, 10, 43, 20, A0, 0D, 06, 10, 35, FF, 01, FF, 02, - A0, 0D, 06, 10, 34, F7, 7F, 00, 00, - A0, 0D, 06, 6A, 42, F8, 10, FF, FF, - A0, 0D, 03, 6A, 16, 00, - A0, 0D, 03, 6A, 15, 01, - A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F + A0, 0D, 06, 10, 34, F7, 7F, 00, 00 } -NXP_RF_CONF_BLK_6={ - 20, 02, AF, 17, +NXP_RF_CONF_BLK_5={ + 20, 02, 7F, 10, + A0, 0D, 06, 6A, 42, F8, 10, FF, FF, A0, 0D, 06, 8C, 42, 88, 10, FF, FF, - A0, 0D, 06, 8C, 4A, 33, 07, 01, 07, - A0, 0D, 03, 8C, 16, 00, - A0, 0D, 03, 8C, 15, 00, A0, 0D, 06, 92, 42, 90, 10, FF, FF, - A0, 0D, 06, 92, 4A, 31, 07, 01, 07, - A0, 0D, 03, 92, 16, 00, - A0, 0D, 03, 92, 15, 00, A0, 0D, 03, 24, 41, 40, - A0, 0D, 06, 24, 42, 00, 03, F3, F3, + A0, 0D, 06, 24, 42, 00, 02, F2, F2, A0, 0D, 03, 28, 41, 40, A0, 0D, 03, 8A, 41, 40, A0, 0D, 03, 90, 41, 40, A0, 0D, 03, 08, 40, 10, A0, 0D, 06, 08, 45, C0, 82, 00, 00, - A0, 0D, 06, 0A, 44, A3, 90, 03, 00, A0, 0D, 06, 0A, 45, 80, 40, 00, 00, A0, 0D, 06, 0A, 30, C8, 00, 64, 00, A0, 0D, 06, 0A, 2F, AF, 05, 80, 17, - A0, 0D, 03, 0A, 48, 10, A0, 0D, 06, 0A, 34, 26, 65, E5, 03, A0, 0D, 06, 0A, 33, 0F, 01, 00, 70, A0, 0D, 03, 0A, 40, 00 @@ -522,24 +436,24 @@ NXP_SET_CONFIG_ALWAYS=0x01 # A0F2 - SWP_SVDD_ON_CFG # CLIF_ANA_CLK_MAN_REG Phone ON A01D # CLIF_ANA_CLK_MAN_REG Phone OFF A01E -NXP_CORE_CONF_EXTN={20, 02, 6F, 13, - A0, 02, 01, 01, - A0, 09, 02, 90, 01, - A0, 12, 01, 00, - A0, 40, 01, 01, +NXP_CORE_CONF_EXTN={20, 02, 75, 13, + A0, 02, 01, 01, + A0, 09, 02, 90, 01, + A0, 12, 01, 00, + A0, 40, 01, 01, A0, 41, 01, 05, - A0, 42, 01, 16, + A0, 42, 01, 0F, A0, 43, 01, 03, - A0, 5E, 01, 01, - A0, 61, 01, 53, - A0, 96, 01, 01, - A0, DD, 01, 2D, - A0, EC, 01, 01, - A0, ED, 01, 00, - A0, F2, 01, 00, + A0, 5E, 01, 01, + A0, 61, 01, 53, + A0, 68, 01, 01, + A0, 96, 01, 01, + A0, DD, 01, 2D, + A0, EC, 01, 01, + A0, ED, 01, 00, + A0, F2, 01, 00, + A0, CA, 07, 02, 00, 1F, 01, 1F, 0F, 20, A0, 47, 02, 00, 27, - A0, CD, 01, 1F, - A0, CB, 01, 10, A0, 1D, 11, 57, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00, A0, 1E, 11, 18, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00 }