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potter: update config files

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This commit is contained in:
Vachounet
2017-04-08 09:19:48 +02:00
parent b45cd2de75
commit a7d4bd842e
18 changed files with 2629 additions and 2008 deletions
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68
configs/camera/ov16860_chromatix.xml → configs/camera/mot_imx362_chromatix.xml
View File

@@ -1,5 +1,5 @@
<!--
Copyright (c) 2015 Qualcomm Technologies, Inc.
Copyright (c) 2016 Qualcomm Technologies, Inc.
All Rights Reserved.
Confidential and Proprietary - Qualcomm Technologies, Inc.
-->
@@ -79,46 +79,56 @@ special_mode_mask values:
<ChromatixConfigurationRoot>
<CommonChromatixInfo>
<ChromatixName special_mode_mask="0">
<ISPCommon>ov16860_common</ISPCommon>
<PostProc>ov16860_postproc</PostProc>
<CPPPreview>ov16860_cpp_snapshot</CPPPreview>
<CPPSnapshot>ov16860_cpp_snapshot</CPPSnapshot>
<ISPCommon>mot_imx362_common</ISPCommon>
<PostProc>mot_imx362_postproc</PostProc>
</ChromatixName>
<ChromatixName special_mode_mask="MOT_4K_VIDEO">
<ISPVideo>ov16860_video_4k</ISPVideo>
<CPPVideo>ov16860_cpp_video_4k</CPPVideo>
<CPPLiveshot>ov16860_cpp_liveshot_4k</CPPLiveshot>
<A3Video>ov16860_4k_video_3a</A3Video>
<ISPVideo>mot_imx362_video_4k</ISPVideo>
<CPPVideo>mot_imx362_cpp_video_4k</CPPVideo>
<A3Video>mot_imx362_4k_video_3a</A3Video>
</ChromatixName>
<ChromatixName special_mode_mask="MOT_ALTM_IHDR_VIDEO">
<ISPVideo>ov16860_default_ihdr_video</ISPVideo>
<CPPLiveshot>ov16860_cpp_liveshot_ihdr</CPPLiveshot>
<A3Video>ov16860_ihdr_video_3a</A3Video>
<ISPVideo>mot_imx362_ihdr_video</ISPVideo>
<A3Video>mot_imx362_ihdr_video_3a</A3Video>
</ChromatixName>
<ChromatixName special_mode_mask="MOT_4K_IHDR_VIDEO">
<ISPVideo>ov16860_ihdr_video_4k</ISPVideo>
<CPPLiveshot>ov16860_cpp_liveshot_4k_ihdr</CPPLiveshot>
<A3Video>ov16860_4k_ihdr_video_3a</A3Video>
<ISPVideo>mot_imx362_ihdr_video_4k</ISPVideo>
<A3Video>mot_imx362_4k_ihdr_video_3a</A3Video>
</ChromatixName>
</CommonChromatixInfo>
<ResolutionChromatixInfo>
<ChromatixName sensor_resolution_index="0" special_mode_mask="0">
<ISPPreview>ov16860_snapshot</ISPPreview>
<ISPSnapshot>ov16860_snapshot</ISPSnapshot>
<ISPVideo>ov16860_default_video</ISPVideo>
<CPPVideo>ov16860_cpp_video</CPPVideo>
<CPPLiveshot>ov16860_cpp_liveshot</CPPLiveshot>
<A3Preview>ov16860_zsl_preview_3a</A3Preview>
<A3Video>ov16860_zsl_video_3a</A3Video>
<ISPPreview>mot_imx362_snapshot</ISPPreview>
<ISPSnapshot>mot_imx362_snapshot</ISPSnapshot>
<ISPVideo>mot_imx362_default_video</ISPVideo>
<CPPPreview>mot_imx362_cpp_preview</CPPPreview>
<CPPSnapshot>mot_imx362_cpp_snapshot</CPPSnapshot>
<CPPVideo>mot_imx362_cpp_video</CPPVideo>
<CPPLiveshot>mot_imx362_cpp_liveshot</CPPLiveshot>
<A3Preview>mot_imx362_fullsize_preview_3a</A3Preview>
<A3Video>mot_imx362_fullsize_video_3a</A3Video>
</ChromatixName>
<ChromatixName sensor_resolution_index="1" special_mode_mask="0">
<ISPPreview>ov16860_hfr_120</ISPPreview>
<ISPSnapshot>ov16860_hfr_120</ISPSnapshot>
<ISPVideo>ov16860_hfr_120</ISPVideo>
<CPPLiveshot>ov16860_cpp_liveshot</CPPLiveshot>
<CPPVideo>ov16860_cpp_hfr_120</CPPVideo>
<A3Preview>ov16860_hfr_120_3a</A3Preview>
<A3Video>ov16860_hfr_120_3a</A3Video>
<ISPPreview>mot_imx362_hfr_60</ISPPreview>
<ISPSnapshot>mot_imx362_hfr_60</ISPSnapshot>
<ISPVideo>mot_imx362_hfr_60</ISPVideo>
<CPPPreview>mot_imx362_cpp_hfr_60</CPPPreview>
<CPPSnapshot>mot_imx362_cpp_hfr_60</CPPSnapshot>
<CPPVideo>mot_imx362_cpp_hfr_60</CPPVideo>
<CPPLiveshot>mot_imx362_cpp_hfr_60</CPPLiveshot>
<A3Preview>mot_imx362_hfr_60_3a</A3Preview>
<A3Video>mot_imx362_hfr_60_3a</A3Video>
</ChromatixName>
<ChromatixName sensor_resolution_index="2" special_mode_mask="0">
<ISPPreview>mot_imx362_hfr_120</ISPPreview>
<ISPSnapshot>mot_imx362_hfr_120</ISPSnapshot>
<ISPVideo>mot_imx362_hfr_120</ISPVideo>
<CPPPreview>mot_imx362_cpp_hfr_120</CPPPreview>
<CPPSnapshot>mot_imx362_cpp_hfr_120</CPPSnapshot>
<CPPVideo>mot_imx362_cpp_hfr_120</CPPVideo>
<CPPLiveshot>mot_imx362_cpp_hfr_120</CPPLiveshot>
<A3Preview>mot_imx362_hfr_120_3a</A3Preview>
<A3Video>mot_imx362_hfr_120_3a</A3Video>
</ChromatixName>
</ResolutionChromatixInfo>
</ChromatixConfigurationRoot>

40
configs/camera/ov5693_chromatix.xml → configs/camera/mot_ov5695_chromatix.xml
View File

@@ -1,5 +1,5 @@
<!--
Copyright (c) 2015 Qualcomm Technologies, Inc.
Copyright (c) 2016 Qualcomm Technologies, Inc.
All Rights Reserved.
Confidential and Proprietary - Qualcomm Technologies, Inc.
-->
@@ -79,31 +79,31 @@ special_mode_mask values:
<ChromatixConfigurationRoot>
<CommonChromatixInfo>
<ChromatixName special_mode_mask="0">
<ISPCommon>ov5693_common</ISPCommon>
<PostProc>ov5693_postproc</PostProc>
<CPPPreview>ov5693_cpp_snapshot</CPPPreview>
<CPPSnapshot>ov5693_cpp_snapshot</CPPSnapshot>
<CPPLiveshot>ov5693_cpp_liveshot</CPPLiveshot>
<ISPCommon>mot_ov5695_common</ISPCommon>
<PostProc>mot_ov5695_postproc</PostProc>
<CPPPreview>mot_ov5695_cpp_snapshot</CPPPreview>
<CPPSnapshot>mot_ov5695_cpp_snapshot</CPPSnapshot>
<CPPLiveshot>mot_ov5695_cpp_liveshot</CPPLiveshot>
</ChromatixName>
</CommonChromatixInfo>
<ResolutionChromatixInfo>
<ChromatixName sensor_resolution_index="0" special_mode_mask="0">
<ISPPreview>ov5693_snapshot</ISPPreview>
<ISPSnapshot>ov5693_snapshot</ISPSnapshot>
<ISPVideo>ov5693_default_video</ISPVideo>
<ISPLiveshot>ov5693_snapshot</ISPLiveshot>
<CPPVideo>ov5693_cpp_video</CPPVideo>
<A3Preview>ov5693_snapshot_3a</A3Preview>
<A3Video>ov5693_default_video_3a</A3Video>
<ISPPreview>mot_ov5695_snapshot</ISPPreview>
<ISPSnapshot>mot_ov5695_snapshot</ISPSnapshot>
<ISPVideo>mot_ov5695_default_video</ISPVideo>
<ISPLiveshot>mot_ov5695_snapshot</ISPLiveshot>
<CPPVideo>mot_ov5695_cpp_video</CPPVideo>
<A3Preview>mot_ov5695_snapshot_3a</A3Preview>
<A3Video>mot_ov5695_default_video_3a</A3Video>
</ChromatixName>
<ChromatixName sensor_resolution_index="1" special_mode_mask="0">
<ISPPreview>ov5693_hfr_120</ISPPreview>
<ISPSnapshot>ov5693_hfr_120</ISPSnapshot>
<ISPVideo>ov5693_hfr_120</ISPVideo>
<ISPLiveshot>ov5693_hfr_120</ISPLiveshot>
<CPPVideo>ov5693_cpp_hfr_120</CPPVideo>
<A3Preview>ov5693_hfr_120_3a</A3Preview>
<A3Video>ov5693_hfr_120_3a</A3Video>
<ISPPreview>mot_ov5695_hfr_120</ISPPreview>
<ISPSnapshot>mot_ov5695_hfr_120</ISPSnapshot>
<ISPVideo>mot_ov5695_hfr_120</ISPVideo>
<ISPLiveshot>mot_ov5695_hfr_120</ISPLiveshot>
<CPPVideo>mot_ov5695_cpp_hfr_120</CPPVideo>
<A3Preview>mot_ov5695_hfr_120_3a</A3Preview>
<A3Video>mot_ov5695_hfr_120_3a</A3Video>
</ChromatixName>
</ResolutionChromatixInfo>
</ChromatixConfigurationRoot>

0
configs/camera/msm8953_mot_camera.xml → configs/camera/msm8953_mot_potter_camera.xml
View File

615
configs/libnfc-nxp.conf
View File

@@ -1,11 +1,9 @@
###############################################################################
## Modified by Motorola Mobility LLC
## Version : 3.5.2 (2016/06/21)
## added RF Blk 4 (21 to 22) and rf blk 5 (from 47 to 77) and rf blk 6 (from 10 to 00)
## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
## CLIF_ANA_TX_AMPLITUDE_REG_TYPE_B_TERMINAL_M
## CLIF_ANA_TX_AMPLITUDE_REG_TYPE_B_TERMINAL_M change 90 to 00
## Version : 3.7 (2016/09/27)
## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn548)
## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn548)
###############################################################################
# Application options
@@ -29,10 +27,14 @@ NXP_NFC_DEV_NODE="/dev/pn544"
###############################################################################
# Extension for Mifare reader enable
# Disabled - 0x00
# Enabled - 0x01
MIFARE_READER_ENABLE=0x01
###############################################################################
# Vzw Feature enable
# Disabled - 0x00
# Enabled - 0x01
VZW_FEATURE_ENABLE=0x01
###############################################################################
@@ -44,7 +46,7 @@ NXP_FW_NAME="libpn548ad_fw.so"
#define CLK_SRC_XTAL 1
#define CLK_SRC_PLL 2
NXP_SYS_CLK_SRC_SEL=0x01
NXP_SYS_CLK_SRC_SEL=0x02
###############################################################################
# System clock frequency selection configuration
@@ -55,13 +57,12 @@ NXP_SYS_CLK_SRC_SEL=0x01
#define CLK_FREQ_38_4MHZ 5
#define CLK_FREQ_52MHZ 6
NXP_SYS_CLK_FREQ_SEL=0x04
NXP_SYS_CLK_FREQ_SEL=0x02
###############################################################################
# The timeout value to be used for clock request acknowledgment
# min value = 0x01 to max = 0x06
NXP_SYS_CLOCK_TO_CFG=0x01
# min value = 0x01 (1.33 ms) to max = 0x06 (2.98 ms)
NXP_SYS_CLOCK_TO_CFG=0x06
###############################################################################
# NXP proprietary settings
@@ -79,145 +80,514 @@ NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01}
###############################################################################
# Standby enable settings
# Disabled - 0x00
# Enabled - 0x01
NXP_CORE_STANDBY={2F, 00, 01, 01}
###############################################################################
# NXP TVDD configurations settings
# Allow NFCC to configure External TVDD, There are currently three
#configurations (1, 2 and 3) are supported, out of them only one can be
#supported.
# Allow NFCC to configure the external TVDD
# Three configurations (0x01, 0x02 and 0x03) are supported
# Only one shall be selected (hardware dependancy)
# Config 1: VUP connected to VBAT
# Config 2: VUP connected to external 5V
# Config 3: TVDD connected to external 5V
NXP_EXT_TVDD_CFG=0x02
#config1:SLALM, 3.3V for both RM and CM
NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00}
#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
#monitoring 5V from DCDC, 4.7V for both RM and CM, DCDCWaitTime=4.2ms
NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 64, 0A}
#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
#No dual sim
NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 64, 01}
#Dual SIM
#NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, E4, 0A}
#config3: use DCDC in CE, use Tx_Pwr_Req, SLALM, monitoring 5V from DCDC,
#DCDCWaitTime=4.2ms
NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
# NXP RF ALMSL configuration settings for FW VERSION = 10.01.1B
#
# A0, 0D, 03, 00, 40, 01 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG
# A0, 0D, 06, 00, FF, 05, 04, 06, 00 RF_CLIF_CFG_BOOT SMU_PMU_REG (0x40024010)
# A0, 0D, 06, 00, 35, FF, 01, FF, 02 RF_CLIF_CFG_BOOT CLIF_AGC_INPUT_REG
# A0, 0D, 06, 00, 33, 07, 40, 00, 00 RF_CLIF_CFG_BOOT CLIF_AGC_CONFIG0_REG
# A0, 0D, 03, 02, 40, 00 RF_CLIF_CFG_IDLE CLIF_ANA_NFCLD_REG
# A0, 0D, 03, 04, 43, 20 RF_CLIF_CFG_INITIATOR CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 03, 04, 47, 02 RF_CLIF_CFG_INITIATOR CLIF_ANA_AGC_REG
# A0, 0D, 06, 04, 35, F4, 01, F4, 01 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG
# A0, 0D, 06, 04, FF, 05, 00, 00, 00 RF_CLIF_CFG_INITIATOR SMU_PMU_REG (0x40024010)
# A0, 0D, 06, 05, 45, 80, 40, 00, 00 RF_CLIF_CFG_INITIATOR CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 05, 35, FF, 01, FF, 02 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG
# A0, 0D, 06, 05, 33, 07, 40, 00, 00 RF_CLIF_CFG_INITIATOR CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 06, 44, A3, 90, 03, 00 RF_CLIF_CFG_TARGET CLIF_ANA_RX_REG
# A0, 0D, 03, 06, 47, 02 RF_CLIF_CFG_TARGET CLIF_ANA_AGC_REG
# A0, 0D, 06, 06, 35, FF, 03, FF, 03 RF_CLIF_CFG_TARGET CLIF_AGC_INPUT_REG
# A0, 0D, 06, 06, 34, F7, 7F, 00, 10 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 06, 33, 03, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 06, 30, C8, 00, 64, 00 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 06, 2F, AF, 05, 80, 17 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 06, 03, 00, 6D, 00, 20 RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 03, 06, 43, 20 RF_CLIF_CFG_TARGET CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 06, 06, 42, 00, 02, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 06, 41, 40 RF_CLIF_CFG_TARGET CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 03, 06, 37, 08 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
# A0, 0D, 03, 06, 16, 00 RF_CLIF_CFG_TARGET CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 06, 15, 00 RF_CLIF_CFG_TARGET CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 06, 3F, 04 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG
# A0, 0D, 03, 06, 80, 03 RF_CLIF_CFG_TARGET CLIF_SPARE_REG
# A0, 0D, 06, 06, FF, 05, 00, 00, 00 RF_CLIF_CFG_TARGET SMU_PMU_REG (0x40024010)
# A0, 0D, 03, 07, 3F, 00 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG
# A0, 0D, 06, 07, 35, FF, 01, FF, 02 RF_CLIF_CFG_TARGET CLIF_AGC_INPUT_REG
# A0, 0D, 06, 07, 33, 07, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 18, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 18, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 1C, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 1C, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 20, 4A, 00, 00, 00, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 20, 42, 88, 10, FF, FF RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 20, 16, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 20, 15, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 22, 44, 22, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_ANA_RX_REG
# A0, 0D, 06, 22, 2D, 50, 44, 0C, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 32, 03, 40, 3D RF_CLIF_CFG_BR_106_I_TXA CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 32, 16, 00 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 32, 15, 01 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 32, 0D, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 32, 14, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 32, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 34, 2D, 24, 47, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 34, 34, 00, 00, EC, 03 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 34, 33, 0F, 01, 01, 70 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG0_REG
# A0, 0D, 04, 34, 44, 21, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG
# A0, 0D, 06, 38, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 38, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 38, 16, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 38, 15, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 3A, 44, 26, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 3A, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 3A, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 3C, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 3C, 16, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 3C, 15, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 3E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 3E, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 3E, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG0_REG
# A0, 0D, 06, 40, 42, F0, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 40, 0D, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_DATA_MOD_REG
# A0, 0D, 03, 40, 14, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_SYMBOL23_MOD_REG
# A0, 0D, 06, 40, 4A, 12, 07, 00, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 40, 16, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 40, 15, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 42, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 42, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 42, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 42, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG0_REG
# A0, 0D, 04, 46, 44, 26, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 46, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 44, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 44, 16, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 44, 15, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 4A, 44, 21, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 48, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 48, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 48, 16, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 48, 15, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 4E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 4C, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 4C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 4C, 16, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 4C, 15, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 04, 52, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 52, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 50, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 50, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 50, 16, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 50, 15, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 56, 44, 22, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 5C, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 54, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 54, 16, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 54, 15, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 5A, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 5A, 16, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 5A, 15, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 98, 2F, CF, 05, 80, 17 RF_CLIF_CFG_GTM_B CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 98, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_B CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 9A, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_FELICA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 30, 44, 12, 90, 03, 00 RF_CLIF_CFG_TECHNO_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 6C, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 70, 2F, 8F, 05, 80, 12 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 70, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 03, 70, 2E, 40 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_CM_CONFIG_REG
# A0, 0D, 03, 70, 45, 30 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 70, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 74, 2F, 6F, 05, 80, 12 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 74, 30, D5, 00, 40, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 74, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 78, 2F, 3F, 07, 80, C1 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 78, 30, 50, 00, 10, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 78, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 7C, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 7C, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 7C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 80, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 80, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 80, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 84, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 84, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 84, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 88, 2F, B1, 05, 80, 17 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 06, 88, 30, A8, 00, 64, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 88, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 8E, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 06, 94, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 03, 10, 43, 20 RF_CLIF_CFG_T_ACTIVE CLIF_ANA_PBF_CONTROL_REG
# A0, 0D, 06, 10, 35, FF, 01, FF, 02 RF_CLIF_CFG_T_ACTIVE CLIF_AGC_INPUT_REG
# A0, 0D, 06, 10, 34, F7, 7F, 00, 00 RF_CLIF_CFG_T_ACTIVE CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 6A, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 6A, 16, 00 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 6A, 15, 01 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 06, 8C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 8C, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 8C, 16, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 8C, 15, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 06, 92, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 92, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
# A0, 0D, 03, 92, 16, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
# A0, 0D, 03, 92, 15, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
# A0, 0D, 03, 24, 41, 40 RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 06, 24, 42, 00, 02, FF, FF RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 28, 41, 40 RF_CLIF_CFG_TECHNO_T_TXB CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 03, 8A, 41, 40 RF_CLIF_CFG_BR_212_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 03, 90, 41, 40 RF_CLIF_CFG_BR_424_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG
# A0, 0D, 03, 08, 40, 10 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_NFCLD_REG
# A0, 0D, 06, 08, 45, C0, 82, 00, 00 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 0A, 44, A3, 90, 03, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_RX_REG
# A0, 0D, 06, 0A, 45, 80, 40, 00, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CM_CONFIG_REG
# A0, 0D, 06, 0A, 30, C8, 00, 64, 00 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
# A0, 0D, 06, 0A, 2F, AF, 05, 80, 17 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_CONFIG_REG
# A0, 0D, 03, 0A, 48, 10 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG
# A0, 0D, 06, 0A, 34, 26, 65, E5, 03 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG1_REG
# A0, 0D, 06, 0A, 33, 0F, 01, 00, 70 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG0_REG
# A0, 0D, 03, 0A, 40, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_NFCLD_REG
#
# *** ALMSL FW VERSION = 10.01.1B ***
NXP_RF_CONF_BLK_1={
20, 02, 1E, 2,
A0, 1D, 11, 54, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
A0, 0D, 06, 06, 03, 00, 6F, 00, 20
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_2={
20, 02, 13, 02,
20, 02, FA, 20,
A0, 0D, 03, 00, 40, 03,
A0, 0D, 06, 00, FF, 05, 04, 06, 00,
A0, 0D, 06, 00, 35, 00, 00, FF, 02,
A0, 0D, 06, 00, 33, 07, 40, 00, 00,
A0, 0D, 03, 02, 40, 00,
A0, 0D, 03, 04, 43, 20,
A0, 0D, 03, 04, 47, 02,
A0, 0D, 06, 04, 35, F4, 01, F4, 01,
A0, 0D, 06, 04, FF, 05, 00, 00, 00,
A0, 0D, 06, 05, 45, 80, 40, 00, 00,
A0, 0D, 06, 05, 35, FF, 01, FF, 02,
A0, 0D, 06, 05, 33, 07, 40, 00, 00,
A0, 0D, 06, 06, 44, A3, 90, 03, 00,
A0, 0D, 03, 06, 47, 02,
A0, 0D, 06, 06, 35, 00, 01, 00, 02,
A0, 0D, 06, 06, 34, F7, 7F, 00, 10,
A0, 0D, 06, 06, 33, 03, 40, 00, 00,
A0, 0D, 06, 06, 30, B0, 00, 10, 00,
A0, 0D, 06, 7C, 30, B0, 00, 10, 00
A0, 0D, 06, 06, 2F, AF, 05, 80, 17,
A0, 0D, 06, 06, 03, 00, 72, 00, 20,
A0, 0D, 03, 06, 43, 20,
A0, 0D, 06, 06, 42, 00, 03, F3, F3,
A0, 0D, 03, 06, 41, 40,
A0, 0D, 03, 06, 37, 08,
A0, 0D, 03, 06, 16, 00,
A0, 0D, 03, 06, 15, 00,
A0, 0D, 03, 06, 3F, 04,
A0, 0D, 03, 06, 80, 03,
A0, 0D, 06, 06, FF, 05, 00, 00, 00,
A0, 0D, 03, 07, 3F, 00,
A0, 0D, 06, 07, 35, FF, 01, FF, 02,
A0, 0D, 06, 07, 33, 07, 40, 00, 00
}
NXP_RF_CONF_BLK_2={
20, 02, F8, 1F,
A0, 0D, 06, 18, 34, 00, 00, E1, 03,
A0, 0D, 06, 18, 33, 0F, 83, 00, 00,
A0, 0D, 06, 1C, 34, 00, 00, E1, 03,
A0, 0D, 06, 1C, 33, 0F, 83, 00, 00,
A0, 0D, 06, 20, 4A, 00, 00, 00, 00,
A0, 0D, 06, 20, 42, 88, 10, FF, FF,
A0, 0D, 03, 20, 16, 00,
A0, 0D, 03, 20, 15, 00,
A0, 0D, 04, 22, 44, 22, 00,
A0, 0D, 06, 22, 2D, 50, 44, 0C, 00,
A0, 0D, 04, 32, 03, 40, 3D,
A0, 0D, 06, 32, 42, F8, 10, FF, FF,
A0, 0D, 03, 32, 16, 00,
A0, 0D, 03, 32, 15, 01,
A0, 0D, 03, 32, 0D, 22,
A0, 0D, 03, 32, 14, 22,
A0, 0D, 06, 32, 4A, 33, 07, 00, 08,
A0, 0D, 06, 34, 2D, 24, 47, 0C, 00,
A0, 0D, 06, 34, 34, 00, 00, EC, 03,
A0, 0D, 06, 34, 33, 0F, 01, 01, 70,
A0, 0D, 04, 34, 44, 22, 00,
A0, 0D, 06, 38, 4A, 33, 07, 00, 08,
A0, 0D, 06, 38, 42, 68, 10, FF, FF,
A0, 0D, 03, 38, 16, 00,
A0, 0D, 03, 38, 15, 00,
A0, 0D, 04, 3A, 44, 26, 00,
A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 3A, 34, 00, 00, E1, 03,
A0, 0D, 06, 3A, 33, 0B, 83, 00, 00,
A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B,
A0, 0D, 06, 3C, 42, 68, 10, FF, FF
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_3={
20, 02, 07, 01,
A0, 0D, 03, 00, 40, 03
20, 02, F9, 20,
A0, 0D, 03, 3C, 16, 00,
A0, 0D, 03, 3C, 15, 00,
A0, 0D, 04, 3E, 44, 26, 00,
A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 3E, 34, 00, 00, E1, 03,
A0, 0D, 06, 3E, 33, 0B, 83, 00, 00,
A0, 0D, 06, 40, 42, F0, 10, FF, FF,
A0, 0D, 03, 40, 0D, 02,
A0, 0D, 03, 40, 14, 02,
A0, 0D, 06, 40, 4A, 12, 07, 00, 00,
A0, 0D, 03, 40, 16, 00,
A0, 0D, 03, 40, 15, 00,
A0, 0D, 04, 42, 44, 26, 00,
A0, 0D, 06, 42, 2D, 15, 47, 0D, 00,
A0, 0D, 06, 42, 34, 00, 00, E1, 03,
A0, 0D, 06, 42, 33, 0B, 83, 00, 00,
A0, 0D, 04, 46, 44, 26, 00,
A0, 0D, 06, 46, 2D, 15, 25, 0D, 00,
A0, 0D, 06, 44, 4A, 21, 07, 00, 07,
A0, 0D, 06, 44, 42, 88, 10, FF, FF,
A0, 0D, 03, 44, 16, 00,
A0, 0D, 03, 44, 15, 00,
A0, 0D, 04, 4A, 44, 21, 00,
A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00,
A0, 0D, 06, 48, 4A, 21, 07, 00, 07,
A0, 0D, 06, 48, 42, 88, 10, FF, FF,
A0, 0D, 03, 48, 16, 00,
A0, 0D, 03, 48, 15, 00,
A0, 0D, 04, 4E, 44, 26, 00,
A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00,
A0, 0D, 06, 4C, 4A, 21, 07, 00, 07,
A0, 0D, 06, 4C, 42, 88, 10, FF, FF
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
# RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG change from 21 to 22
NXP_RF_CONF_BLK_4={
20, 02, 1D, 04,
A0, 0D, 04, 34, 44, 22, 00,
A0, 0D, 04, 46, 44, 22, 00,
A0, 0D, 04, 56, 44, 22, 00,
A0, 0D, 04, 5C, 44, 26, 00
20, 02, F4, 1F,
A0, 0D, 03, 4C, 16, 00,
A0, 0D, 03, 4C, 15, 00,
A0, 0D, 04, 52, 44, 26, 00,
A0, 0D, 06, 52, 2D, 15, 25, 0D, 00,
A0, 0D, 06, 50, 42, 90, 10, FF, FF,
A0, 0D, 06, 50, 4A, 21, 07, 00, 07,
A0, 0D, 03, 50, 16, 00,
A0, 0D, 03, 50, 15, 00,
A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00,
A0, 0D, 04, 56, 44, 22, 00,
A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00,
A0, 0D, 04, 5C, 44, 26, 00,
A0, 0D, 06, 54, 42, 88, 10, FF, FF,
A0, 0D, 06, 54, 4A, 33, 07, 01, 07,
A0, 0D, 03, 54, 16, 00,
A0, 0D, 03, 54, 15, 00,
A0, 0D, 06, 5A, 42, 90, 10, FF, FF,
A0, 0D, 06, 5A, 4A, 31, 07, 01, 07,
A0, 0D, 03, 5A, 16, 00,
A0, 0D, 03, 5A, 15, 00,
A0, 0D, 06, 98, 2F, CF, 05, 80, 17,
A0, 0D, 06, 98, 42, 00, 03, F3, F3,
A0, 0D, 06, 9A, 42, 00, 03, F3, F3,
A0, 0D, 06, 30, 44, 12, 90, 03, 00,
A0, 0D, 06, 6C, 44, A3, 90, 03, 00,
A0, 0D, 06, 6C, 30, CF, 00, 08, 00,
A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C,
A0, 0D, 06, 70, 2F, 8F, 05, 80, 12,
A0, 0D, 06, 70, 30, CF, 00, 08, 00,
A0, 0D, 03, 70, 2E, 40,
A0, 0D, 03, 70, 45, 30
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform, Min_level
# RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG change from 47 to 77
NXP_RF_CONF_BLK_5={
20, 02, 0A, 01,
A0, 0D, 06, 34, 2D, 24, 77, 0C, 00
20, 02, F4, 1C,
A0, 0D, 06, 70, 44, A3, 90, 03, 00,
A0, 0D, 06, 74, 2F, 6F, 05, 80, 12,
A0, 0D, 06, 74, 30, D5, 00, 40, 00,
A0, 0D, 06, 74, 44, A3, 90, 03, 00,
A0, 0D, 06, 78, 2F, 3F, 07, 80, C1,
A0, 0D, 06, 78, 30, 50, 00, 10, 00,
A0, 0D, 06, 78, 44, A3, 90, 03, 00,
A0, 0D, 06, 7C, 2F, CF, 05, 80, 17,
A0, 0D, 06, 7C, 30, B0, 00, 10, 00,
A0, 0D, 06, 7C, 44, A3, 90, 03, 00,
A0, 0D, 06, 80, 2F, CF, 05, 80, 17,
A0, 0D, 06, 80, 30, C8, 00, 64, 00,
A0, 0D, 06, 80, 44, A3, 90, 03, 00,
A0, 0D, 06, 84, 2F, CF, 05, 80, 17,
A0, 0D, 06, 84, 30, C8, 00, 64, 00,
A0, 0D, 06, 84, 44, A3, 90, 03, 00,
A0, 0D, 06, 88, 2F, B1, 05, 80, 17,
A0, 0D, 06, 88, 30, A8, 00, 64, 00,
A0, 0D, 06, 88, 44, A3, 90, 03, 00,
A0, 0D, 06, 8E, 44, 12, 90, 03, 00,
A0, 0D, 06, 94, 44, 12, 90, 03, 00,
A0, 0D, 03, 10, 43, 20,
A0, 0D, 06, 10, 35, FF, 01, FF, 02,
A0, 0D, 06, 10, 34, F7, 7F, 00, 00,
A0, 0D, 06, 6A, 42, F8, 10, FF, FF,
A0, 0D, 03, 6A, 16, 00,
A0, 0D, 03, 6A, 15, 01,
A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
# RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG change from 10 to 00
# RF_CLIF_CFG_BR_106_T_TXB
NXP_RF_CONF_BLK_6={
20, 02, 2E, 05,
A0, 0D, 06, 32, 42, F8, 00, FF, FF,
A0, 0D, 06, 44, 42, 88, 00, FF, FF,
A0, 0D, 06, 54, 42, 88, 00, FF, FF,
A0, 0D, 06, 5A, 42, 90, 00, FF, FF,
A0, 0D, 06, 98, 42, 00, 00, FF, FF
20, 02, AF, 17,
A0, 0D, 06, 8C, 42, 88, 10, FF, FF,
A0, 0D, 06, 8C, 4A, 33, 07, 01, 07,
A0, 0D, 03, 8C, 16, 00,
A0, 0D, 03, 8C, 15, 00,
A0, 0D, 06, 92, 42, 90, 10, FF, FF,
A0, 0D, 06, 92, 4A, 31, 07, 01, 07,
A0, 0D, 03, 92, 16, 00,
A0, 0D, 03, 92, 15, 00,
A0, 0D, 03, 24, 41, 40,
A0, 0D, 06, 24, 42, 00, 03, F3, F3,
A0, 0D, 03, 28, 41, 40,
A0, 0D, 03, 8A, 41, 40,
A0, 0D, 03, 90, 41, 40,
A0, 0D, 03, 08, 40, 10,
A0, 0D, 06, 08, 45, C0, 82, 00, 00,
A0, 0D, 06, 0A, 44, A3, 90, 03, 00,
A0, 0D, 06, 0A, 45, 80, 40, 00, 00,
A0, 0D, 06, 0A, 30, C8, 00, 64, 00,
A0, 0D, 06, 0A, 2F, AF, 05, 80, 17,
A0, 0D, 03, 0A, 48, 10,
A0, 0D, 06, 0A, 34, 26, 65, E5, 03,
A0, 0D, 06, 0A, 33, 0F, 01, 00, 70,
A0, 0D, 03, 0A, 40, 00
}
###############################################################################
## Set configuration optimization decision setting
## Enable = 0x01
## Disable = 0x00
NXP_SET_CONFIG_ALWAYS=0x01
###############################################################################
# Core configuration extensions
# It includes
# Wired mode settings A0ED, A0EE
# Tag Detector A040, A041, A043
# Low Power mode A007
# Clock settings A002, A003
# PbF settings A008
NXP_CORE_CONF_EXTN={20, 02, 1D, 07,
A0, EC, 01, 01,
A0, ED, 01, 00,
A0, 5E, 01, 01,
A0, 40, 01, 01,
A0, DD, 01, 2D,
A0, 41, 01, 02,
A0, 96, 01, 01
}
# A0, 41, 01, 02,
# A0, 43, 01, 04,
# A0, 02, 01, 01,
# A0, 03, 01, 11,
# A0, 07, 01, 03,
# A0, 08, 01, 01
# }
# A002 - Disable/Enable Clock Request
# A009 - Time-out before standby
# A012 - NFCEE interface 2 configuration
# A040 - Low Power Card Detector Enable
# A041 - Low Power Card Detector Threshold
# A042 - Low Power Card Detector Sampling
# A043 - Low Power Card Detector Hybrid
# A05E - Send RID automatically in Jewel Reader mode
# A061 - Retry after LPCD
# A096 - Notification for all AIDs in Card emulation mode
# A0DD - Number of retry for DWP
# A0EC - Disable/Enable SWP1 interface
# A0ED - Disable/Enable SWP2 interface
# A0F2 - SWP_SVDD_ON_CFG
# CLIF_ANA_CLK_MAN_REG Phone ON A01D
# CLIF_ANA_CLK_MAN_REG Phone OFF A01E
NXP_CORE_CONF_EXTN={20, 02, 6F, 13,
A0, 02, 01, 01,
A0, 09, 02, 90, 01,
A0, 12, 01, 00,
A0, 40, 01, 01,
A0, 41, 01, 03,
A0, 42, 01, 16,
A0, 43, 01, 08,
A0, 5E, 01, 01,
A0, 61, 01, 53,
A0, 96, 01, 01,
A0, DD, 01, 2D,
A0, EC, 01, 01,
A0, ED, 01, 00,
A0, F2, 01, 00,
A0, 47, 02, 00, 27,
A0, CD, 01, 1F,
A0, CB, 01, 10,
A0, 1D, 11, 57, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
A0, 1E, 11, 18, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00
}
###############################################################################
# Core configuration rf field filter settings to enable set to 01 to disable set to 00 last bit
NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 01
}
# Core configuration RF Field notification filter
# Disabled - 0x00
# Enabled - 0x01
NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00}
###############################################################################
# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00
# I2C fragmentation
# Disabled - 0x00
# Enabled - 0x01
NXP_I2C_FRAGMENTATION_ENABLED=0x00
###############################################################################
# Core configuration settings
NXP_CORE_CONF={ 20, 02, 31, 0F,
28, 01, 00,
21, 01, 00,
30, 01, 08,
31, 01, 03,
33, 04, 01, 02, 03, 04,
54, 01, 06,
50, 01, 02,
5B, 01, 00,
60, 01, 0E,
80, 01, 01,
81, 01, 01,
82, 01, 0E,
18, 01, 01,
32, 01, 60,
38, 01, 01
# It includes
# 18 - Poll Mode NFC-F: PF_BIT_RATE
# 21 - Poll Mode ISO-DEP: PI_BIT_RATE
# 28 - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
# 30 - Lis. Mode NFC-A: LA_BIT_FRAME_SDD
# 31 - Lis. Mode NFC-A: LA_PLATFORM_CONFIG
# 50 - Lis. Mode NFC-F: LF_PROTOCOL_TYPE
# 54 - Lis. Mode NFC-F: LF_CON_BITR_F
# 5B - Lis. Mode ISO-DEP: LI_BIT_RATE
# 60 - Lis. Mode NFC-DEP: LN_WT
# 80 - Other Param.: RF_FIELD_INFO
# 81 - Other Param.: RF_NFCEE_ACTION
# 82 - Other Param.: NFCDEP_OP
NXP_CORE_CONF={20, 02, 2A, 0E,
18, 01, 01,
21, 01, 00,
28, 01, 00,
30, 01, 04,
31, 01, 00,
33, 00,
50, 01, 02,
54, 01, 06,
5B, 01, 00,
60, 01, 0E,
80, 01, 01,
81, 01, 01,
82, 01, 0E,
32, 01, 60
}
###############################################################################
@@ -254,12 +624,15 @@ NXP_NFC_CHIP=0x03
# Enable 0x01
NXP_CE_ROUTE_STRICT_DISABLE=0x01
#Timeout in secs to get NFCEE Discover notification
###############################################################################
# Timeout in secs to get NFCEE Discover notification
NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20
NXP_DEFAULT_NFCEE_TIMEOUT=0x06
#Timeout in secs
###############################################################################
# SWP Reader feature
# Timeout in seconds
NXP_SWP_RD_START_TIMEOUT=0x0A
#Timeout in secs
@@ -297,7 +670,7 @@ DEFAULT_MIFARE_CLT_ROUTE=0x02
# bit pos 2 = Battery Off
# bit pos 3 = Screen Lock
# bit pos 4 = Screen Off
DEFAULT_AID_PWR_STATE=0x9
DEFAULT_AID_PWR_STATE=0x19
###############################################################################
#Set the Mifare Desfire Power state :
@@ -324,11 +697,13 @@ DEFAULT_MIFARE_CLT_PWR_STATE=0x1B
# AID_MATCHING_L 0x01
# AID_MATCHING_K 0x02
AID_MATCHING_PLATFORM=0x01
###############################################################################
#CHINA_TIANJIN_RF_SETTING
#Enable 0x01
#Disable 0x00
NXP_CHINA_TIANJIN_RF_ENABLED=0x01
###############################################################################
#SWP_SWITCH_TIMEOUT_SETTING
# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
@@ -336,26 +711,44 @@ NXP_CHINA_TIANJIN_RF_ENABLED=0x01
# No Timeout 0x00
# 10 millisecond timeout 0x0A
NXP_SWP_SWITCH_TIMEOUT=0x0A
###############################################################################
#Dynamic RSSI feature enable
# Disable 0x00
# Enable 0x01
NXP_AGC_DEBUG_ENABLE=0x00
###############################################################################
# UICC mode supported
# Disable 0x00
# Enable 0x01
NXP_DUAL_UICC_ENABLE=0x00
###############################################################################
#Config to allow adding aids
#NFC on/off is required after this config
#1 = enabling adding aid to NFCC routing table.
#0 = disabling adding aid to NFCC routing table.
NXP_ENABLE_ADD_AID=0x01
################################################################################
###############################################################################
# Enable/Disable checking default proto SE Id
# Disable 0x00
# Enable 0x01
NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01
###############################################################################
# UICC mode supported
# Disable 0x00
# Enable 0x01
NXP_DUAL_UICC_ENABLE=0x00
################################################################################
# Restriction of Type A UICC baud rate
# Default supported - 0x00
# 212kbps maximum supported - 0x01
# 424kbps maximum supported - 0x02
# 848kbps maximum supported - 0x03
NXP_TYPEA_UICC_BAUD_RATE=0x00
################################################################################
# Restriction of Type B UICC baud rate
# Default supported - 0x00
# 212kbps maximum supported - 0x01
# 424kbps maximum supported - 0x02
# 848kbps maximum supported - 0x03
NXP_TYPEB_UICC_BAUD_RATE=0x00

346
configs/libnfc-nxp_ds.conf
View File

@@ -1,346 +0,0 @@
###############################################################################
## Modified by Motorola Mobility LLC
## Version : 3.5.2 (2016/05/26)
## Dual SIM with switcher HW
## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
###############################################################################
# Application options
# Logging Levels
# NXPLOG_DEFAULT_LOGLEVEL 0x01
# ANDROID_LOG_DEBUG 0x03
# ANDROID_LOG_WARN 0x02
# ANDROID_LOG_ERROR 0x01
# ANDROID_LOG_SILENT 0x00
#
NXPLOG_EXTNS_LOGLEVEL=0x03
NXPLOG_NCIHAL_LOGLEVEL=0x03
NXPLOG_NCIX_LOGLEVEL=0x03
NXPLOG_NCIR_LOGLEVEL=0x03
NXPLOG_FWDNLD_LOGLEVEL=0x03
NXPLOG_TML_LOGLEVEL=0x03
###############################################################################
# Nfc Device Node name
NXP_NFC_DEV_NODE="/dev/pn544"
###############################################################################
# Extension for Mifare reader enable
MIFARE_READER_ENABLE=0x01
###############################################################################
# Vzw Feature enable
VZW_FEATURE_ENABLE=0x01
###############################################################################
# File name for Firmware
NXP_FW_NAME="libpn548ad_fw.so"
###############################################################################
# System clock source selection configuration
#define CLK_SRC_XTAL 1
#define CLK_SRC_PLL 2
NXP_SYS_CLK_SRC_SEL=0x01
###############################################################################
# System clock frequency selection configuration
#define CLK_FREQ_13MHZ 1
#define CLK_FREQ_19_2MHZ 2
#define CLK_FREQ_24MHZ 3
#define CLK_FREQ_26MHZ 4
#define CLK_FREQ_38_4MHZ 5
#define CLK_FREQ_52MHZ 6
NXP_SYS_CLK_FREQ_SEL=0x04
###############################################################################
# The timeout value to be used for clock request acknowledgment
# min value = 0x01 to max = 0x06
NXP_SYS_CLOCK_TO_CFG=0x01
###############################################################################
# NXP proprietary settings
NXP_ACT_PROP_EXTN={2F, 02, 00}
###############################################################################
# NFC forum profile settings
NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
###############################################################################
# NFCC Configuration Control
# Allow NFCC to manage RF Config 0x01
# Don't allow NFCC to manage RF Config 0x00
NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01}
###############################################################################
# Standby enable settings
NXP_CORE_STANDBY={2F, 00, 01, 01}
###############################################################################
# NXP TVDD configurations settings
# Allow NFCC to configure External TVDD, There are currently three
#configurations (1, 2 and 3) are supported, out of them only one can be
#supported.
NXP_EXT_TVDD_CFG=0x02
#config1:SLALM, 3.3V for both RM and CM
NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00}
#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
#monitoring 5V from DCDC, 4.7V for both RM and CM, DCDCWaitTime=4.2ms
# No Dual SIM
#NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 64, 0A}
# Dual SIM - bit 7 of the second value should be set to 1
NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, E4, 0A}
#config3: use DCDC in CE, use Tx_Pwr_Req, SLALM, monitoring 5V from DCDC,
#DCDCWaitTime=4.2ms
NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 64, 0A}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_1={
20, 02, 1E, 2,
A0, 1D, 11, 54, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
A0, 0D, 06, 06, 03, 00, 73, 00, 20
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_2={
20, 02, 13, 02,
A0, 0D, 06, 06, 30, B0, 00, 10, 00,
A0, 0D, 06, 7C, 30, B0, 00, 10, 00
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_3={
20, 02, 07, 01,
A0, 0D, 03, 00, 40, 03
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_4={
#}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform, Min_level
#NXP_RF_CONF_BLK_5={
#}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_6={
#}
###############################################################################
## Set configuration optimization decision setting
## Enable = 0x01
## Disable = 0x00
NXP_SET_CONFIG_ALWAYS=0x01
###############################################################################
# Core configuration extensions
# It includes
# Wired mode settings A0ED, A0EE
# Tag Detector A040, A041, A043
# Low Power mode A007
# Clock settings A002, A003
# PbF settings A008
NXP_CORE_CONF_EXTN={20, 02, 1D, 07,
A0, EC, 01, 11,
A0, ED, 01, 00,
A0, 5E, 01, 01,
A0, 40, 01, 01,
A0, DD, 01, 2D,
A0, 41, 01, 02,
A0, 96, 01, 01
}
# A0, 41, 01, 02,
# A0, 43, 01, 04,
# A0, 02, 01, 01,
# A0, 03, 01, 11,
# A0, 07, 01, 03,
# A0, 08, 01, 01
# }
###############################################################################
# Core configuration rf field filter settings to enable set to 01 to disable set to 00 last bit
NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 01
}
###############################################################################
# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00
NXP_I2C_FRAGMENTATION_ENABLED=0x00
###############################################################################
# Core configuration settings
NXP_CORE_CONF={ 20, 02, 31, 0F,
28, 01, 00,
21, 01, 00,
30, 01, 08,
31, 01, 03,
33, 04, 01, 02, 03, 04,
54, 01, 06,
50, 01, 02,
5B, 01, 00,
60, 01, 0E,
80, 01, 01,
81, 01, 01,
82, 01, 0E,
18, 01, 01,
32, 01, 60,
38, 01, 01
}
###############################################################################
# Mifare Classic Key settings
#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
# A0, 52, 06, D3, F7, D3, F7, D3, F7,
# A0, 53, 06, FF, FF, FF, FF, FF, FF,
# A0, 54, 06, 00, 00, 00, 00, 00, 00}
###############################################################################
# Default SE Options
# No secure element 0x00
# eSE 0x01
# UICC 0x02
NXP_DEFAULT_SE=0x02
###############################################################################
#Enable SWP full power mode when phone is power off
NXP_SWP_FULL_PWR_ON=0x00
###############################################################################
#### Select the CHIP ####
#PN547C2 0x01
#PN65T 0x02
#PN548AD 0x03
#PN66T 0x04
NXP_NFC_CHIP=0x03
###############################################################################
# CE when Screen state is locked
# Disable 0x00
# Enable 0x01
NXP_CE_ROUTE_STRICT_DISABLE=0x01
#Timeout in secs to get NFCEE Discover notification
NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20
NXP_DEFAULT_NFCEE_TIMEOUT=0x06
#Timeout in secs
NXP_SWP_RD_START_TIMEOUT=0x0A
#Timeout in secs
NXP_SWP_RD_TAG_OP_TIMEOUT=0x01
###############################################################################
#Set the default AID route Location :
#This settings will be used when application does not set this parameter
# host 0x00
# eSE 0x01
# UICC 0x02
DEFAULT_AID_ROUTE=0x00
###############################################################################
#Set the Mifare Desfire route Location :
#This settings will be used when application does not set this parameter
# host 0x00
# eSE 0x01
# UICC 0x02
DEFAULT_DESFIRE_ROUTE=0x02
###############################################################################
#Set the Mifare CLT route Location :
#This settings will be used when application does not set this parameter
# host 0x00
# eSE 0x01
# UICC 0x02
DEFAULT_MIFARE_CLT_ROUTE=0x02
###############################################################################
#Set the default AID Power state :
#This settings will be used when application does not set this parameter
# bit pos 0 = Switch On
# bit pos 1 = Switch Off
# bit pos 2 = Battery Off
# bit pos 3 = Screen Lock
# bit pos 4 = Screen Off
DEFAULT_AID_PWR_STATE=0x9
###############################################################################
#Set the Mifare Desfire Power state :
#This settings will be used when application does not set this parameter
# bit pos 0 = Switch On
# bit pos 1 = Switch Off
# bit pos 2 = Battery Off
# bit pos 3 = Screen Lock
# bit pos 4 = Screen Off
DEFAULT_DESFIRE_PWR_STATE=0x1B
###############################################################################
#Set the Mifare CLT Power state :
#This settings will be used when application does not set this parameter
# bit pos 0 = Switch On
# bit pos 1 = Switch Off
# bit pos 2 = Battery Off
# bit pos 3 = Screen Lock
# bit pos 4 = Screen Off
DEFAULT_MIFARE_CLT_PWR_STATE=0x1B
###############################################################################
# AID Matching platform options
# AID_MATCHING_L 0x01
# AID_MATCHING_K 0x02
AID_MATCHING_PLATFORM=0x01
###############################################################################
#CHINA_TIANJIN_RF_SETTING
#Enable 0x01
#Disable 0x00
NXP_CHINA_TIANJIN_RF_ENABLED=0x01
###############################################################################
#SWP_SWITCH_TIMEOUT_SETTING
# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
# Timeout in milliseconds, for example
# No Timeout 0x00
# 10 millisecond timeout 0x0A
NXP_SWP_SWITCH_TIMEOUT=0x0A
###############################################################################
#Dynamic RSSI feature enable
# Disable 0x00
# Enable 0x01
NXP_AGC_DEBUG_ENABLE=0x00
###############################################################################
#Config to allow adding aids
#NFC on/off is required after this config
#1 = enabling adding aid to NFCC routing table.
#0 = disabling adding aid to NFCC routing table.
NXP_ENABLE_ADD_AID=0x01
################################################################################
# Enable/Disable checking default proto SE Id
# Disable 0x00
# Enable 0x01
NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01
###############################################################################
# UICC mode supported
# Disable 0x00
# Enable 0x01
NXP_DUAL_UICC_ENABLE=0x01

276
configs/media_codecs_performance.xml
View File

@@ -1,138 +1,138 @@
<?xml version="1.0" encoding="utf-8" ?>
<!-- Copyright (c) 2016, The Linux Foundation. All rights reserved.
Not a Contribution.
Copyright 2016 The Android Open Source Project
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<MediaCodecs>
<Encoders>
<MediaCodec name="OMX.google.h263.encoder" type="video/3gpp" update="true">
<Limit name="measured-frame-rate-176x144" range="374-377" />
</MediaCodec>
<MediaCodec name="OMX.google.h264.encoder" type="video/avc" update="true">
<Limit name="measured-frame-rate-320x240" range="245-250" />
<Limit name="measured-frame-rate-720x480" range="96-97" />
<Limit name="measured-frame-rate-1280x720" range="48-48" />
<Limit name="measured-frame-rate-1920x1080" range="24-24" />
</MediaCodec>
<MediaCodec name="OMX.google.mpeg4.encoder" type="video/mp4v-es" update="true">
<Limit name="measured-frame-rate-176x144" range="382-385" />
</MediaCodec>
<MediaCodec name="OMX.google.vp8.encoder" type="video/x-vnd.on2.vp8" update="true">
<Limit name="measured-frame-rate-320x180" range="111-112" />
<Limit name="measured-frame-rate-640x360" range="37-37" />
<Limit name="measured-frame-rate-1280x720" range="33-33" />
<Limit name="measured-frame-rate-1920x1080" range="19-19" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.avc" type="video/avc" update="true">
<Limit name="measured-frame-rate-320x240" range="282-285" />
<Limit name="measured-frame-rate-720x480" range="83-83" />
<Limit name="measured-frame-rate-1280x720" range="36-36" />
<Limit name="measured-frame-rate-1920x1080" range="32-32" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.h263" type="video/3gpp" update="true">
<Limit name="measured-frame-rate-176x144" range="355-358" />
<Limit name="measured-frame-rate-352x288" range="283-284" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.hevc" type="video/hevc" update="true">
<Limit name="measured-frame-rate-320x240" range="269-272" />
<Limit name="measured-frame-rate-720x480" range="83-83" />
<Limit name="measured-frame-rate-1280x720" range="36-36" />
<Limit name="measured-frame-rate-1920x1080" range="32-32" />
<Limit name="measured-frame-rate-3840x2160" range="9-9" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.mpeg4" type="video/mp4v-es" update="true">
<Limit name="measured-frame-rate-176x144" range="356-359" />
<Limit name="measured-frame-rate-352x288" range="277-278" />
<Limit name="measured-frame-rate-640x480" range="149-150" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.vp8" type="video/x-vnd.on2.vp8" update="true">
<Limit name="measured-frame-rate-320x180" range="267-271" />
<Limit name="measured-frame-rate-640x360" range="126-126" />
<Limit name="measured-frame-rate-1280x720" range="34-34" />
<Limit name="measured-frame-rate-1920x1080" range="30-30" />
</MediaCodec>
</Encoders>
<Decoders>
<MediaCodec name="OMX.google.h263.decoder" type="video/3gpp" update="true">
<Limit name="measured-frame-rate-176x144" range="185-191" />
</MediaCodec>
<MediaCodec name="OMX.google.h264.decoder" type="video/avc" update="true">
<Limit name="measured-frame-rate-320x240" range="317-326" />
<Limit name="measured-frame-rate-720x480" range="132-133" />
<Limit name="measured-frame-rate-1280x720" range="57-57" />
<Limit name="measured-frame-rate-1920x1080" range="24-24" />
</MediaCodec>
<MediaCodec name="OMX.google.hevc.decoder" type="video/hevc" update="true">
<Limit name="measured-frame-rate-352x288" range="460-471" />
<Limit name="measured-frame-rate-640x360" range="238-240" />
<Limit name="measured-frame-rate-720x480" range="218-220" />
<Limit name="measured-frame-rate-1280x720" range="97-98" />
<Limit name="measured-frame-rate-1920x1080" range="54-54" />
</MediaCodec>
<MediaCodec name="OMX.google.mpeg4.decoder" type="video/mp4v-es" update="true">
<Limit name="measured-frame-rate-176x144" range="205-210" />
</MediaCodec>
<MediaCodec name="OMX.google.vp8.decoder" type="video/x-vnd.on2.vp8" update="true">
<Limit name="measured-frame-rate-320x180" range="631-634" />
<Limit name="measured-frame-rate-640x360" range="179-182" />
<Limit name="measured-frame-rate-1280x720" range="40-41" />
<Limit name="measured-frame-rate-1920x1080" range="17-17" />
</MediaCodec>
<MediaCodec name="OMX.google.vp9.decoder" type="video/x-vnd.on2.vp9" update="true">
<Limit name="measured-frame-rate-320x180" range="376-382" />
<Limit name="measured-frame-rate-640x360" range="183-183" />
<Limit name="measured-frame-rate-1280x720" range="90-91" />
<Limit name="measured-frame-rate-1920x1080" range="50-50" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.avc" type="video/avc" update="true">
<Limit name="measured-frame-rate-320x240" range="270-275" />
<Limit name="measured-frame-rate-720x480" range="230-233" />
<Limit name="measured-frame-rate-1280x720" range="133-134" />
<Limit name="measured-frame-rate-1920x1080" range="53-53" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.h263" type="video/3gpp" update="true">
<Limit name="measured-frame-rate-176x144" range="422-429" />
<Limit name="measured-frame-rate-352x288" range="427-431" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.hevc" type="video/hevc" update="true">
<Limit name="measured-frame-rate-352x288" range="341-345" />
<Limit name="measured-frame-rate-640x360" range="266-269" />
<Limit name="measured-frame-rate-720x480" range="250-252" />
<Limit name="measured-frame-rate-1280x720" range="120-121" />
<Limit name="measured-frame-rate-1920x1080" range="56-56" />
<Limit name="measured-frame-rate-3840x2160" range="13-13" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.mpeg4" type="video/mp4v-es" update="true">
<Limit name="measured-frame-rate-176x144" range="428-433" />
<Limit name="measured-frame-rate-480x360" range="409-412" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.vp8" type="video/x-vnd.on2.vp8" update="true">
<Limit name="measured-frame-rate-320x180" range="434-436" />
<Limit name="measured-frame-rate-640x360" range="357-358" />
<Limit name="measured-frame-rate-1280x720" range="321-321" />
<Limit name="measured-frame-rate-1920x1080" range="148-148" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.vp9" type="video/x-vnd.on2.vp9" update="true">
<Limit name="measured-frame-rate-320x180" range="422-424" />
<Limit name="measured-frame-rate-640x360" range="305-306" />
<Limit name="measured-frame-rate-1280x720" range="308-309" />
<Limit name="measured-frame-rate-1920x1080" range="161-161" />
<Limit name="measured-frame-rate-3840x2160" range="36-36" />
</MediaCodec>
</Decoders>
</MediaCodecs>
<?xml version="1.0" encoding="utf-8" ?>
<!-- Copyright (c) 2016, The Linux Foundation. All rights reserved.
Not a Contribution.
Copyright 2016 The Android Open Source Project
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<MediaCodecs>
<Encoders>
<MediaCodec name="OMX.google.h263.encoder" type="video/3gpp" update="true">
<Limit name="measured-frame-rate-176x144" range="374-377" />
</MediaCodec>
<MediaCodec name="OMX.google.h264.encoder" type="video/avc" update="true">
<Limit name="measured-frame-rate-320x240" range="245-250" />
<Limit name="measured-frame-rate-720x480" range="96-97" />
<Limit name="measured-frame-rate-1280x720" range="48-48" />
<Limit name="measured-frame-rate-1920x1080" range="24-24" />
</MediaCodec>
<MediaCodec name="OMX.google.mpeg4.encoder" type="video/mp4v-es" update="true">
<Limit name="measured-frame-rate-176x144" range="382-385" />
</MediaCodec>
<MediaCodec name="OMX.google.vp8.encoder" type="video/x-vnd.on2.vp8" update="true">
<Limit name="measured-frame-rate-320x180" range="111-112" />
<Limit name="measured-frame-rate-640x360" range="37-37" />
<Limit name="measured-frame-rate-1280x720" range="33-33" />
<Limit name="measured-frame-rate-1920x1080" range="19-19" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.avc" type="video/avc" update="true">
<Limit name="measured-frame-rate-320x240" range="282-285" />
<Limit name="measured-frame-rate-720x480" range="83-83" />
<Limit name="measured-frame-rate-1280x720" range="36-36" />
<Limit name="measured-frame-rate-1920x1080" range="32-32" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.h263" type="video/3gpp" update="true">
<Limit name="measured-frame-rate-176x144" range="355-358" />
<Limit name="measured-frame-rate-352x288" range="283-284" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.hevc" type="video/hevc" update="true">
<Limit name="measured-frame-rate-320x240" range="269-272" />
<Limit name="measured-frame-rate-720x480" range="83-83" />
<Limit name="measured-frame-rate-1280x720" range="36-36" />
<Limit name="measured-frame-rate-1920x1080" range="32-32" />
<Limit name="measured-frame-rate-3840x2160" range="9-9" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.mpeg4" type="video/mp4v-es" update="true">
<Limit name="measured-frame-rate-176x144" range="356-359" />
<Limit name="measured-frame-rate-352x288" range="277-278" />
<Limit name="measured-frame-rate-640x480" range="149-150" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.encoder.vp8" type="video/x-vnd.on2.vp8" update="true">
<Limit name="measured-frame-rate-320x180" range="267-271" />
<Limit name="measured-frame-rate-640x360" range="126-126" />
<Limit name="measured-frame-rate-1280x720" range="34-34" />
<Limit name="measured-frame-rate-1920x1080" range="30-30" />
</MediaCodec>
</Encoders>
<Decoders>
<MediaCodec name="OMX.google.h263.decoder" type="video/3gpp" update="true">
<Limit name="measured-frame-rate-176x144" range="185-191" />
</MediaCodec>
<MediaCodec name="OMX.google.h264.decoder" type="video/avc" update="true">
<Limit name="measured-frame-rate-320x240" range="317-326" />
<Limit name="measured-frame-rate-720x480" range="132-133" />
<Limit name="measured-frame-rate-1280x720" range="57-57" />
<Limit name="measured-frame-rate-1920x1080" range="24-24" />
</MediaCodec>
<MediaCodec name="OMX.google.hevc.decoder" type="video/hevc" update="true">
<Limit name="measured-frame-rate-352x288" range="460-471" />
<Limit name="measured-frame-rate-640x360" range="238-240" />
<Limit name="measured-frame-rate-720x480" range="218-220" />
<Limit name="measured-frame-rate-1280x720" range="97-98" />
<Limit name="measured-frame-rate-1920x1080" range="54-54" />
</MediaCodec>
<MediaCodec name="OMX.google.mpeg4.decoder" type="video/mp4v-es" update="true">
<Limit name="measured-frame-rate-176x144" range="205-210" />
</MediaCodec>
<MediaCodec name="OMX.google.vp8.decoder" type="video/x-vnd.on2.vp8" update="true">
<Limit name="measured-frame-rate-320x180" range="631-634" />
<Limit name="measured-frame-rate-640x360" range="179-182" />
<Limit name="measured-frame-rate-1280x720" range="40-41" />
<Limit name="measured-frame-rate-1920x1080" range="17-17" />
</MediaCodec>
<MediaCodec name="OMX.google.vp9.decoder" type="video/x-vnd.on2.vp9" update="true">
<Limit name="measured-frame-rate-320x180" range="376-382" />
<Limit name="measured-frame-rate-640x360" range="183-183" />
<Limit name="measured-frame-rate-1280x720" range="90-91" />
<Limit name="measured-frame-rate-1920x1080" range="50-50" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.avc" type="video/avc" update="true">
<Limit name="measured-frame-rate-320x240" range="270-275" />
<Limit name="measured-frame-rate-720x480" range="230-233" />
<Limit name="measured-frame-rate-1280x720" range="133-134" />
<Limit name="measured-frame-rate-1920x1080" range="53-53" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.h263" type="video/3gpp" update="true">
<Limit name="measured-frame-rate-176x144" range="422-429" />
<Limit name="measured-frame-rate-352x288" range="427-431" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.hevc" type="video/hevc" update="true">
<Limit name="measured-frame-rate-352x288" range="341-345" />
<Limit name="measured-frame-rate-640x360" range="266-269" />
<Limit name="measured-frame-rate-720x480" range="250-252" />
<Limit name="measured-frame-rate-1280x720" range="120-121" />
<Limit name="measured-frame-rate-1920x1080" range="56-56" />
<Limit name="measured-frame-rate-3840x2160" range="13-13" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.mpeg4" type="video/mp4v-es" update="true">
<Limit name="measured-frame-rate-176x144" range="428-433" />
<Limit name="measured-frame-rate-480x360" range="409-412" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.vp8" type="video/x-vnd.on2.vp8" update="true">
<Limit name="measured-frame-rate-320x180" range="434-436" />
<Limit name="measured-frame-rate-640x360" range="357-358" />
<Limit name="measured-frame-rate-1280x720" range="321-321" />
<Limit name="measured-frame-rate-1920x1080" range="148-148" />
</MediaCodec>
<MediaCodec name="OMX.qcom.video.decoder.vp9" type="video/x-vnd.on2.vp9" update="true">
<Limit name="measured-frame-rate-320x180" range="422-424" />
<Limit name="measured-frame-rate-640x360" range="305-306" />
<Limit name="measured-frame-rate-1280x720" range="308-309" />
<Limit name="measured-frame-rate-1920x1080" range="161-161" />
<Limit name="measured-frame-rate-3840x2160" range="36-36" />
</MediaCodec>
</Decoders>
</MediaCodecs>

315
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<?xml version="1.0" encoding="utf-8"?>
<!-- Copyright (C) 2013 The Android Open Source Project
Copyright (C) 2015-2016 The Linux Foundation. All rights reserved.
Not a contribution.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
-->
<!DOCTYPE MediaSettings [
<!ELEMENT MediaSettings (CamcorderProfiles,
EncoderOutputFileFormat+,
VideoEncoderCap+,
AudioEncoderCap+,
VideoDecoderCap,
AudioDecoderCap)>
<!ELEMENT CamcorderProfiles (EncoderProfile+, ImageEncoding+, ImageDecoding, Camera)>
<!ELEMENT EncoderProfile (Video, Audio)>
<!ATTLIST EncoderProfile quality (high|low) #REQUIRED>
<!ATTLIST EncoderProfile fileFormat (mp4|3gp) #REQUIRED>
<!ATTLIST EncoderProfile duration (30|60) #REQUIRED>
<!ATTLIST EncoderProfile cameraId (0|1) #REQUIRED>
<!ELEMENT Video EMPTY>
<!ATTLIST Video codec (h264|h263|m4v) #REQUIRED>
<!ATTLIST Video bitRate CDATA #REQUIRED>
<!ATTLIST Video width CDATA #REQUIRED>
<!ATTLIST Video height CDATA #REQUIRED>
<!ATTLIST Video frameRate CDATA #REQUIRED>
<!ELEMENT Audio EMPTY>
<!ATTLIST Audio codec (amrnb|amrwb|aac|lpcm) #REQUIRED>
<!ATTLIST Audio bitRate CDATA #REQUIRED>
<!ATTLIST Audio sampleRate CDATA #REQUIRED>
<!ATTLIST Audio channels (1|2|6) #REQUIRED>
<!ELEMENT ImageEncoding EMPTY>
<!ATTLIST ImageEncoding quality (90|80|70|60|50|40) #REQUIRED>
<!ELEMENT ImageDecoding EMPTY>
<!ATTLIST ImageDecoding memCap CDATA #REQUIRED>
<!ELEMENT Camera EMPTY>
<!ELEMENT EncoderOutputFileFormat EMPTY>
<!ATTLIST EncoderOutputFileFormat name (mp4|3gp) #REQUIRED>
<!ELEMENT VideoEncoderCap EMPTY>
<!ATTLIST VideoEncoderCap name (h264|h263|m4v|wmv) #REQUIRED>
<!ATTLIST VideoEncoderCap enabled (true|false) #REQUIRED>
<!ATTLIST VideoEncoderCap minBitRate CDATA #REQUIRED>
<!ATTLIST VideoEncoderCap maxBitRate CDATA #REQUIRED>
<!ATTLIST VideoEncoderCap minFrameWidth CDATA #REQUIRED>
<!ATTLIST VideoEncoderCap maxFrameWidth CDATA #REQUIRED>
<!ATTLIST VideoEncoderCap minFrameHeight CDATA #REQUIRED>
<!ATTLIST VideoEncoderCap maxFrameHeight CDATA #REQUIRED>
<!ATTLIST VideoEncoderCap minFrameRate CDATA #REQUIRED>
<!ATTLIST VideoEncoderCap maxFrameRate CDATA #REQUIRED>
<!ELEMENT AudioEncoderCap EMPTY>
<!ATTLIST AudioEncoderCap name (amrnb|amrwb|aac|heaac|aaceld|wma|lpcm) #REQUIRED>
<!ATTLIST AudioEncoderCap enabled (true|false) #REQUIRED>
<!ATTLIST AudioEncoderCap minBitRate CDATA #REQUIRED>
<!ATTLIST AudioEncoderCap maxBitRate CDATA #REQUIRED>
<!ATTLIST AudioEncoderCap minSampleRate CDATA #REQUIRED>
<!ATTLIST AudioEncoderCap maxSampleRate CDATA #REQUIRED>
<!ATTLIST AudioEncoderCap minChannels (1|2|6) #REQUIRED>
<!ATTLIST AudioEncoderCap maxChannels (1|2|6) #REQUIRED>
<!ELEMENT VideoDecoderCap EMPTY>
<!ATTLIST VideoDecoderCap name (wmv) #REQUIRED>
<!ATTLIST VideoDecoderCap enabled (true|false) #REQUIRED>
<!ELEMENT AudioDecoderCap EMPTY>
<!ATTLIST AudioDecoderCap name (wma) #REQUIRED>
<!ATTLIST AudioDecoderCap enabled (true|false) #REQUIRED>
]>
<!--
This file is used to declare the multimedia profiles and capabilities
on an android-powered device.
-->
<MediaSettings>
<!-- Each camcorder profile defines a set of predefined configuration parameters -->
<!-- Back Camera -->
<CamcorderProfiles cameraId="0">
<EncoderProfile quality="low" fileFormat="3gp" duration="30">
<Video codec="h264"
bitRate="128000"
width="320"
height="240"
frameRate="15" />
<Audio codec="amrnb"
bitRate="12200"
sampleRate="8000"
channels="1" />
</EncoderProfile>
<EncoderProfile quality="high" fileFormat="mp4" duration="10">
<Video codec="h264"
bitRate="17000000"
width="1920"
height="1080"
frameRate="30" />
<Audio codec="aac"
bitRate="128000"
sampleRate="48000"
channels="2" />
</EncoderProfile>
<EncoderProfile quality="qvga" fileFormat="3gp" duration="30">
<Video codec="h264"
bitRate="128000"
width="320"
height="240"
frameRate="15" />
<Audio codec="amrnb"
bitRate="12200"
sampleRate="8000"
channels="1" />
</EncoderProfile>
<EncoderProfile quality="480p" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="6000000"
width="720"
height="480"
frameRate="30" />
<Audio codec="aac"
bitRate="128000"
sampleRate="48000"
channels="2" />
</EncoderProfile>
<EncoderProfile quality="720p" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="10000000"
width="1280"
height="720"
frameRate="30" />
<Audio codec="aac"
bitRate="128000"
sampleRate="48000"
channels="2" />
</EncoderProfile>
<EncoderProfile quality="1080p" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="17000000"
width="1920"
height="1080"
frameRate="30" />
<Audio codec="aac"
bitRate="128000"
sampleRate="48000"
channels="2" />
</EncoderProfile>
<EncoderProfile quality="timelapselow" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="512000"
width="320"
height="240"
frameRate="30" />
<!-- audio setting is ignored -->
<Audio codec="amrnb"
bitRate="12200"
sampleRate="8000"
channels="1" />
</EncoderProfile>
<EncoderProfile quality="timelapsehigh" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="17000000"
width="1920"
height="1080"
frameRate="30" />
<!-- audio setting is ignored -->
<Audio codec="aac"
bitRate="128000"
sampleRate="48000"
channels="2" />
</EncoderProfile>
<EncoderProfile quality="timelapseqvga" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="512000"
width="320"
height="240"
frameRate="30" />
<!-- audio setting is ignored -->
<Audio codec="amrnb"
bitRate="12200"
sampleRate="8000"
channels="1" />
</EncoderProfile>
<EncoderProfile quality="timelapse480p" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="6000000"
width="640"
height="480"
frameRate="30" />
<!-- audio setting is ignored -->
<Audio codec="aac"
bitRate="128000"
sampleRate="48000"
channels="2" />
</EncoderProfile>
<EncoderProfile quality="timelapse720p" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="10000000"
width="1280"
height="720"
frameRate="30" />
<!-- audio setting is ignored -->
<Audio codec="aac"
bitRate="128000"
sampleRate="48000"
channels="2" />
</EncoderProfile>
<EncoderProfile quality="timelapse1080p" fileFormat="mp4" duration="30">
<Video codec="h264"
bitRate="17000000"
width="1920"
height="1080"
frameRate="30" />
<!-- audio setting is ignored -->
<Audio codec="aac"
bitRate="128000"
sampleRate="48000"
channels="2" />
</EncoderProfile>
<ImageEncoding quality="95" />
<ImageEncoding quality="80" />
<ImageEncoding quality="70" />
<ImageDecoding memCap="20000000" />
</CamcorderProfiles>
<EncoderOutputFileFormat name="3gp" />
<EncoderOutputFileFormat name="mp4" />
<!--
If a codec is not enabled, it is invisible to the applications
In other words, the applications won't be able to use the codec
or query the capabilities of the codec at all if it is disabled
-->
<VideoEncoderCap name="h264" enabled="true"
minBitRate="64000" maxBitRate="60000000"
minFrameWidth="176" maxFrameWidth="3840"
minFrameHeight="144" maxFrameHeight="2160"
minFrameRate="15" maxFrameRate="60" />
<VideoEncoderCap name="h263" enabled="true"
minBitRate="64000" maxBitRate="2000000"
minFrameWidth="176" maxFrameWidth="720"
minFrameHeight="144" maxFrameHeight="480"
minFrameRate="15" maxFrameRate="30" />
<VideoEncoderCap name="m4v" enabled="true"
minBitRate="64000" maxBitRate="20000000"
minFrameWidth="176" maxFrameWidth="1920"
minFrameHeight="144" maxFrameHeight="1080"
minFrameRate="15" maxFrameRate="30" />
<AudioEncoderCap name="aac" enabled="true"
minBitRate="8000" maxBitRate="156000"
minSampleRate="8000" maxSampleRate="48000"
minChannels="1" maxChannels="2" />
<AudioEncoderCap name="heaac" enabled="true"
minBitRate="8000" maxBitRate="128000"
minSampleRate="16000" maxSampleRate="48000"
minChannels="1" maxChannels="2" />
<AudioEncoderCap name="aaceld" enabled="true"
minBitRate="16000" maxBitRate="384000"
minSampleRate="16000" maxSampleRate="48000"
minChannels="1" maxChannels="2" />
<AudioEncoderCap name="amrwb" enabled="true"
minBitRate="6600" maxBitRate="23850"
minSampleRate="16000" maxSampleRate="16000"
minChannels="1" maxChannels="1" />
<AudioEncoderCap name="amrnb" enabled="true"
minBitRate="5525" maxBitRate="12200"
minSampleRate="8000" maxSampleRate="8000"
minChannels="1" maxChannels="1" />
<!--
FIXME:
We do not check decoder capabilities at present
At present, we only check whether windows media is visible
for TEST applications. For other applications, we do
not perform any checks at all.
-->
<!-- IKVPREL2KK-2424 Disable WMV and WMA support -->
<VideoDecoderCap name="wmv" enabled="false"/>
<AudioDecoderCap name="wma" enabled="false"/>
</MediaSettings>

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