msm8953-common: libshims: add shim for android_memset32
* memset32.S and android_memset.S taken from Q
This commit is contained in:
Jan Altensen
committed by
Jorge Lucas
Jorge Lucas
parent
75fce9194b
commit
545bc491b3
@@ -84,6 +84,11 @@ function blob_fixup() {
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sed -i 's/group system input 9015/group system uhid input 9015/' "${2}"
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;;
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# memset shim
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vendor/bin/charge_only_mode)
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patchelf --add-needed libmemset_shim.so "${2}"
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;;
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# qsap shim
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vendor/lib64/libmdmcutback.so)
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patchelf --add-needed libqsap_shim.so "${2}"
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@@ -91,6 +96,7 @@ function blob_fixup() {
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vendor/lib/libmot_gpu_mapper.so)
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sed -i "s/libgui/libwui/" "${2}"
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;;
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# Fix missing symbols
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vendor/lib64/libril-qc-hal-qmi.so)
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18
libshims/Android.bp
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18
libshims/Android.bp
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@@ -0,0 +1,18 @@
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cc_library {
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name: "libmemset_shim",
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vendor: true,
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target: {
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android_arm: {
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srcs: ["memset32.S"],
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sanitize: {
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misc_undefined: ["integer"],
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},
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},
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android_arm64: {
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srcs: ["android_memset.S"],
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sanitize: {
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misc_undefined: ["integer"],
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},
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},
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},
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}
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211
libshims/android_memset.S
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211
libshims/android_memset.S
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@@ -0,0 +1,211 @@
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/* Copyright (c) 2012, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the Linaro nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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* Unaligned accesses
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*
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*/
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/* By default we assume that the DC instruction can be used to zero
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data blocks more efficiently. In some circumstances this might be
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unsafe, for example in an asymmetric multiprocessor environment with
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different DC clear lengths (neither the upper nor lower lengths are
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safe to use). */
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#define dst x0
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#define count x2
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#define tmp1 x3
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#define tmp1w w3
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#define tmp2 x4
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#define tmp2w w4
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#define zva_len_x x5
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#define zva_len w5
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#define zva_bits_x x6
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#define A_l x1
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#define A_lw w1
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#define tmp3w w9
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#define ENTRY(f) \
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.text; \
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.globl f; \
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.align 0; \
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.type f, %function; \
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f: \
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.cfi_startproc \
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#define END(f) \
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.cfi_endproc; \
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.size f, .-f; \
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ENTRY(android_memset16)
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ands A_lw, A_lw, #0xffff
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b.eq .Lzero_mem
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orr A_lw, A_lw, A_lw, lsl #16
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b .Lexpand_to_64
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END(android_memset16)
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ENTRY(android_memset32)
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cmp A_lw, #0
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b.eq .Lzero_mem
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.Lexpand_to_64:
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orr A_l, A_l, A_l, lsl #32
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.Ltail_maybe_long:
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cmp count, #64
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b.ge .Lnot_short
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.Ltail_maybe_tiny:
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cmp count, #15
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b.le .Ltail15tiny
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.Ltail63:
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ands tmp1, count, #0x30
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b.eq .Ltail15
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add dst, dst, tmp1
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cmp tmp1w, #0x20
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b.eq 1f
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b.lt 2f
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stp A_l, A_l, [dst, #-48]
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1:
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stp A_l, A_l, [dst, #-32]
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2:
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stp A_l, A_l, [dst, #-16]
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.Ltail15:
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and count, count, #15
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add dst, dst, count
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stp A_l, A_l, [dst, #-16] /* Repeat some/all of last store. */
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ret
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.Ltail15tiny:
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/* Set up to 15 bytes. Does not assume earlier memory
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being set. */
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tbz count, #3, 1f
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str A_l, [dst], #8
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1:
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tbz count, #2, 1f
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str A_lw, [dst], #4
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1:
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tbz count, #1, 1f
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strh A_lw, [dst], #2
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1:
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ret
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/* Critical loop. Start at a new cache line boundary. Assuming
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* 64 bytes per line, this ensures the entire loop is in one line. */
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.p2align 6
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.Lnot_short:
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neg tmp2, dst
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ands tmp2, tmp2, #15
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b.eq 2f
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/* Bring DST to 128-bit (16-byte) alignment. We know that there's
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* more than that to set, so we simply store 16 bytes and advance by
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* the amount required to reach alignment. */
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sub count, count, tmp2
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stp A_l, A_l, [dst]
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add dst, dst, tmp2
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/* There may be less than 63 bytes to go now. */
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cmp count, #63
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b.le .Ltail63
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2:
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sub dst, dst, #16 /* Pre-bias. */
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sub count, count, #64
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1:
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stp A_l, A_l, [dst, #16]
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stp A_l, A_l, [dst, #32]
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stp A_l, A_l, [dst, #48]
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stp A_l, A_l, [dst, #64]!
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subs count, count, #64
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b.ge 1b
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tst count, #0x3f
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add dst, dst, #16
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b.ne .Ltail63
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ret
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/* For zeroing memory, check to see if we can use the ZVA feature to
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* zero entire 'cache' lines. */
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.Lzero_mem:
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mov A_l, #0
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cmp count, #63
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b.le .Ltail_maybe_tiny
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neg tmp2, dst
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ands tmp2, tmp2, #15
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b.eq 1f
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sub count, count, tmp2
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stp A_l, A_l, [dst]
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add dst, dst, tmp2
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cmp count, #63
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b.le .Ltail63
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1:
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/* For zeroing small amounts of memory, it's not worth setting up
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* the line-clear code. */
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cmp count, #128
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b.lt .Lnot_short
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mrs tmp1, dczid_el0
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tbnz tmp1, #4, .Lnot_short
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mov tmp3w, #4
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and zva_len, tmp1w, #15 /* Safety: other bits reserved. */
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lsl zva_len, tmp3w, zva_len
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.Lzero_by_line:
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/* Compute how far we need to go to become suitably aligned. We're
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* already at quad-word alignment. */
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cmp count, zva_len_x
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b.lt .Lnot_short /* Not enough to reach alignment. */
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sub zva_bits_x, zva_len_x, #1
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neg tmp2, dst
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ands tmp2, tmp2, zva_bits_x
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b.eq 1f /* Already aligned. */
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/* Not aligned, check that there's enough to copy after alignment. */
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sub tmp1, count, tmp2
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cmp tmp1, #64
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ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */
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b.lt .Lnot_short
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/* We know that there's at least 64 bytes to zero and that it's safe
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* to overrun by 64 bytes. */
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mov count, tmp1
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2:
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stp A_l, A_l, [dst]
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stp A_l, A_l, [dst, #16]
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stp A_l, A_l, [dst, #32]
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subs tmp2, tmp2, #64
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stp A_l, A_l, [dst, #48]
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add dst, dst, #64
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b.ge 2b
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/* We've overrun a bit, so adjust dst downwards. */
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add dst, dst, tmp2
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1:
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sub count, count, zva_len_x
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3:
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dc zva, dst
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add dst, dst, zva_len_x
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subs count, count, zva_len_x
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b.ge 3b
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ands count, count, zva_bits_x
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b.ne .Ltail_maybe_long
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ret
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END(android_memset32)
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100
libshims/memset32.S
Normal file
100
libshims/memset32.S
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@@ -0,0 +1,100 @@
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/*
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* Copyright (C) 2006 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* memset32.S
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*
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*/
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.syntax unified
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.text
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.align
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.global android_memset32
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.type android_memset32, %function
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.global android_memset16
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.type android_memset16, %function
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/*
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* Optimized memset32 and memset16 for ARM.
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*
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* void android_memset16(uint16_t* dst, uint16_t value, size_t size);
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* void android_memset32(uint32_t* dst, uint32_t value, size_t size);
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*
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*/
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android_memset16:
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.fnstart
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cmp r2, #1
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bxle lr
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/* expand the data to 32 bits */
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mov r1, r1, lsl #16
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orr r1, r1, r1, lsr #16
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/* align to 32 bits */
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tst r0, #2
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strhne r1, [r0], #2
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subne r2, r2, #2
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.fnend
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android_memset32:
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.fnstart
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.cfi_startproc
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str lr, [sp, #-4]!
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.cfi_def_cfa_offset 4
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.cfi_rel_offset lr, 0
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/* align the destination to a cache-line */
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mov r12, r1
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mov lr, r1
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rsb r3, r0, #0
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ands r3, r3, #0x1C
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beq .Laligned32
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cmp r3, r2
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andhi r3, r2, #0x1C
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sub r2, r2, r3
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/* conditionally writes 0 to 7 words (length in r3) */
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movs r3, r3, lsl #28
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stmiacs r0!, {r1, lr}
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stmiacs r0!, {r1, lr}
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stmiami r0!, {r1, lr}
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movs r3, r3, lsl #2
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strcs r1, [r0], #4
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.Laligned32:
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mov r3, r1
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1: subs r2, r2, #32
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stmiahs r0!, {r1,r3,r12,lr}
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stmiahs r0!, {r1,r3,r12,lr}
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bhs 1b
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add r2, r2, #32
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/* conditionally stores 0 to 30 bytes */
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movs r2, r2, lsl #28
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stmiacs r0!, {r1,r3,r12,lr}
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stmiami r0!, {r1,lr}
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movs r2, r2, lsl #2
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strcs r1, [r0], #4
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strhmi lr, [r0], #2
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ldr lr, [sp], #4
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.cfi_def_cfa_offset 0
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.cfi_restore lr
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bx lr
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.cfi_endproc
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.fnend
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@@ -374,6 +374,7 @@ PRODUCT_PACKAGES += \
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# Shims
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PRODUCT_PACKAGES += \
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libcutils_shim \
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libmemset_shim \
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libqsap_shim
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# USB HAL
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